EE 574: VHDL Modeling and Synthesis – Spring 2005

Vending Machine Project (lab signoff and report due week 7 March 2nd)

Design and synthesize a simple vending machine on the Spartan 3 board with the following features:

Ø The vending machine has five products (candy!). One costs 55 cents, the others cost 60, 65, 70, and 75 cents. Use the slider switches (SW0 thro SW4) to select one of the products.

Ø Use two of seven-segment LED displays to display the cost of the product selected.

Ø The vending machine has a coin-in mechanism that can accept nickel’s, dime’s and quarter’s. Assume a pulse is generated when a coin is entered. Use BTN0, BTN1, BTN2 for the coins. (BTN3 can be used as a master reset but note that the system should automatically reset after dispensing a product)

Ø Use two of the seven-segment LED displays to display the total amount entered (can be as high as 95cents).

Ø When at least the correct amount has been entered the machine should provide the product (turn on the corresponding LD0 thro LD4 to indicate the product is being dispensed)

Ø At the same time or after the product is dispensed, solenoids should activate to provide any change required. (Use LEDs as appropriate to represent nickels or dimes)

A suggestion is to generate a 1 Hz clock for the system timing (derived from the 50MHz xtal)

Make any assumptions you think necessary and provide any additional features to make the machine as user friendly as possible (e.g. coin-lock solenoid to lock out any more coins when the cost of the product is reached).

Target your design to a Xilinx Spartan-3 FPGA. Download to the Spartan-3 starter board and demonstrate correct operation (provide a signoff sheet that describes the features and capabilities of your specific design).

A hierarchical design using a package and multiple components is required.

Make sure you review the project writing guidelines.

Include simulation waveforms demonstrating the correct functional operation of your vending machine. Also include schematics of your synthesized design and include a summary of the FPGA resources used.

Suggestion: Design and test each module (coin_count, display, change_out, etc) separately.

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IEEE Std_logic_Arith Package

If you want to mix integers and std_logic vectors in your design you may find the following conversions useful:

USE ieee.std_logic_arith.ALL;

To convert integer to vector:

Std_logic_vector <= CONV_STD_LOGIC_VECTOR(integer, vector_size);

To convert vector to integer:

integer <= CONV_INTEGER(unsigned or signed vector);

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Multiple Files

You should create multiple files, one for each of your modules (Count.vhd, Display.vhd, Change.vhd, etc).

Each file will have an entity and architecture description for that module.

You will also need a UCF file (see decoder and counter tutorials for examples).

You will also need a package vhd file (Vending_Package.vhd for example) containing your package declarations (constants, subtypes, etc)

You will also need a top level vending.vhd file that includes all your lower level modules as components.

These will be wired together using the Structural Techniques we talked about in Module 1.

You should add all these source files to your project – make sure they are in the right order (package at the top, vending at the bottom, the others in the middle) – drag them if necessary.

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