ECE 574: Modeling and Synthesis of digital systems using Verilog and VHDL

Fall 2009

· Assignments

In this course, you are encouraged to do a substantial amount of independent work. A significant portion of the learning in this course is expected to result from the design projects.

Reading Assignments: you are responsible for reading the material covered in the class and assigned to you for reading from the text book, references, tutorials, and Xilinx/other manuals in order to understand it.

For week 1 read Chapters 1, 2.

Complete the decoder and counter tutorials, and modify the counter – demo this by week 3.

Initial Design Project:

The first design project will involve the design and synthesis of a VGA Display with Serial Interface using VHDL. Report and demonstration due by week 7.

Mid Design Project:

The second design project will involve the design and synthesis of (tbd). Signoff and report due by week 10.

Final Independent Design Project: The final project is a significant design project using VHDL or Verilog. The project will constitute major independent work and is weighed heavily in the grade assigned to the course. You will have the flexibility to choose a project of interest to you after getting approval from the instructor. The design must be synthesizable and must target the Nexys 2board. It must also include a test bench to demonstrate its correct operation. Each student is expected to give a class presentation and submit a written report based on the independent project by the final week.

Signoff Sheet for all projects:

Note: for the demonstration signoff you should have a 1 page signoff sheet that lists in bullet form the main capabilities and operations of your system. The TA can then use this to check off each of the features and operations that you demonstrate. This signoff sheet must be attached to your report.

You will need to submit a Design Project proposal (1 page description) by Week 8.

NO LATE WORK ACCEPTED!

· Computer Usage: general

The project assignments in this course will require use of the Xilinx software tools installed on the ECE department’s PCs and the Xilinx Webpack software and use of the Nexys 2 boards (for home use).

Preparing the written report

A report (no handwritten work accepted) is due for each implementation of the three projects. The reports (due at week 7, week 10, and week 14) should contain the following sections:

· An introduction with a problem statement and a detailed description of your digital design. You should include block diagrams, state diagrams, and other modes of description here.

· A detailed description of your design methodology. This section should discuss the design technique used and describe your implementation. You may use flowcharts or pseudo-code for explaining your design methodology and any hierarchy used in the design.

· A well-commented listing of your VHDL code provided in an Appendix. Should include all packages, source files, configurations that you have developed.

· Description of your testing strategy and a justification for its adequacy. How was the model tested? A description and a listing of any command files used for testing the model (generating patterns, vectors, waveforms etc) or test benches developed. Also provide the results obtained from the various tests you have performed. You should provide any synthesis output in the form of schematics and/or report files showing target resource usage.

· Your conclusions. The conclusions should describe the problems you faced in implementation, solutions you used to solve these problems, any lessons learned from the project, and suggestions for further improvement - or extension.

· List of references/bibliography/appendices.

Grading Guidelines

• [15 pts] Detailed Description of System
• [1 pt] Brief Introduction / Problem Statement
• [2 pts] General Overview of approach to solution
• [3 pts] Block Diagrams (with descriptions)
• [3 pts] State Diagrams (with descriptions)
• [3 pts] Flowcharts / pseudo-code / hierarchy view / other methods of description
• [3 pts] Modeling technique and implementation (translation process of above concepts to code)
• [15 pts] Source Code – VHDL or Verilog (and Picoblaze if required for project)
• Code style and comments (well-commented and tab-indented code!)
• Use of case vs. if, spaghetti code vs. structured, copy & paste vs. code reuse, etc.
• Recognizable implementation of "standard" elements (state machines, counters, clock dividers, decoders)
• Use of packages and other VHDL code structuring elements (sensible use of modularity)
• [15 pts] Testing Strategy (for first project)
• [8 pts] Annotated oscilloscope pictures for VGA and Serial Interface
• [7 pts] Showing of understanding of synthesis output (schematics and/or report files) and target resource usage
• [15 pts] Testing Strategy (for second and final project)
• [12 pts] Test benches and simulation outputs
• [3 pts] Showing of understanding of synthesis output (schematics and/or report files) and target resource usage
• [5 pts] Conclusions
• Problems faced in implementation
• Solutions used to solve problems
• Lessons learned from the project
• Suggestions for further improvements and extensions
• [50 pts] Implementation
• [40 pts] Design works on board and meets requirements
• [10 pts] User-friendliness, features and capabilities
• [10 pts] Possible extra points for really good additional features or capabilities

Final Project Presentation

The following points should be noted about the final presentation (week 13):

1. Each student will give a 5 minute (estimated) presentation related to his/her final project. The presentation should clearly explain the work done, problems encountered, solutions used, and lessons learned from the project. The presentation must be done with transparencies or from the PC.

2. The presentation will constitute 10% weight of the grade allocated to the final independent project. The grade will be based on clarity of presentation, contents, and response to questions from the audience.