ECE 574: Modeling and Synthesis of digital systems using Verilog and VHDL

Fall Semester 2005 (subject to change)

11/27/05:         example DSP code from one student added to the links section

10/18/05:         DSP project now available (see links section below) – signoff and report due Week 11 (Nov 16th)

                        Final Project Proposals due by next week (Oct 26th) – please email a 1 page description

Final project must include a test bench with file I/O. (Extra credit of up to 10% for the final project is possible if a Picoblaze processor with UART and other functions is included in the design).

11/01/05:         Files for simple Picoblaze project added to links section

Note: you will need to obtain the Xilinx Spartan-3 Starter Kit for $99 (containing the 200,00 gate Spartan 3 FPGA) from Xilinx (http://www.xilinx.com/products/spartan3/spot.htm) or Digilent (http://www.digilentinc.com/). It is recommended you buy it directly from Digilent – they also offer a 400,000 gate upgrade version for an additional $20. We only need the 200,000 part for the course but you might find the extra capacity useful if you decide to continue experimenting with the system.

More information about the Starter Kit: (Spartan 3 FPGAs).

You will also need to install on your own PC the Xilinx Webpack software (download from the Xilinx web site – note the OS and system requirements). We will use this board and software throughout the course.

Lecturer.

Dr. R. James Duckworth, AK301, Tel: (508) 831-5204, email: rjduck@wpi.edu

Office Hours: Wednesday afternoon 2.00 to 4.0. Additional times by appointment (send email).

TA. Hauke Daempfling, AK301, email haukex@wpi.edu         

Lectures (Exams)

14 lectures (In AK233, 6.00 pm) starting Wednesday September 7th and ending December 14th

 

Project presentations for final project – December 7

Final exam and final project reports due December 14

Course Description

This is an introductory course on Verilog and VHDL, two standard hardware description languages (HDLs), for students with no background or prior experience with HDLs. In this course we will examine some of the important features of Verilog and VHDL. The course will enable students to design, simulate, model and synthesize digital designs. The dataflow, structural, and behavioral modeling techniques will be discussed and related to how they are used to design combinational and sequential circuits. The use of test benches to exercise and verify the correctness of hardware models will also be described.

Course Projects: Course projects will involve the modeling and synthesis and testing using Xilinx tools. We will be targeting Xilinx FPGA and CPLDs. Students will need to purchase a FPGA or CPLD development board for project assignments. (Other synthesis and simulation tools may be used if these are available to the students at their place of employment.) Students will have the choice of completing assignments in either Verilog or VHDL.

Prerequisites: Logic Circuits and experience with programming in a high-level language (such as C or Pascal) and a computer architecture course such as ECE505.

Textbook: Introductory VHDL From Simulation to Synthesis by Sudhakar Yalamanchilli, Xilinx Design Series, Prentice Hall, ISBN 0-13-080982-9. Note: this textbook includes the Xilinx Student Edition of the Foundation Series Software but do NOT use this software, use the WebPack software instead.

Grading: The final grade is based on the grades for the exam and lab reports. The weight for each part is:

  • Final exam - 30%
  • initial design project (shop calculator design) - 15% (report due week 7)
  • mid design project (DSP Processor) - 15% (report due week 10)
  • final design project - 40% (presentation week 13 and report due week 14)
  • Grade A (> 90), B (75-90), C (60-75)
  • No late work accepted.

Useful Links

·        Assignments and reports – updated with grading guidelines

·        Shop Calculator lab description

·        DSP Processor description

o       Example code

·        Xilinx website

o       Spartan 3 information (http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=Spartan-3)

·        Xilinx Webpack

o       You must first register, and then download and install both WebPack and the MXE tool. Install WebPack and then MXE, and then follow the directions to obtain a license. You cannot run MXE without a license.

·        Digilent Website – manufacturer of Spartan-3 boards boards

·        Picoblaze resources:

o       Xilinx: Picoblaze select the Picoblaze for Spartan 3 and download the design files (includes examples)

o       Read the UART Real Time Clock pdf document – you might want to try running this on your board (will need UCF)

o       Mediatronix website: select the pBlazeIDE and download V3.6 of the assembler/simulator

o       Simple Picoblaze example project files

ece574_pico.vhd is the top level file, ece574.psm is the assembler file, target is Spartan 3 Starter board

·        Tutorials

o       Spartan 3 Decoder Tutorial (For Xilinx synthesis to Spartan 3 board) – equivalent Verilog tutorial

o       Spartan 3 Counter Tutorial (For Xilinx synthesis to Spartan 3 board) – equivalent Verilog tutorial

o       Spartan 3 Decoder Programming Tutorial

 (Spartan 3 Prom generation tutorial – older version)

o       Encoder implementation and simulation (VHDL and Verilog)

o       StateCad Tutorial

o       Using CoreGen and Chipscope

·        VHDL FAQ (http://www.eda.org/comp.lang.vhdl/ ) – very useful resource 

·        Verilog FAQ http://bawankule/verilogfaq/index.htm

·        Paper presented at MSE 2005 on Embedded System Design with FPGAs using HDLs

·        Ten simple rules to follow!

 

Presentations

·        Module 1: Introduction

·        Module 2:  VHDL Basics

·        Module 3: Concurrent Signal Assignment Statements

·        Module 4: The Process Statement

·        Module 5: Sequential Logic

·        Module 6: State Machines

·        Module 7: Miscellaneous

·        Module 8: Test Benches

·        Module 9: VHDL for testing

·        Module 10: VHDL for Modeling

·        Embedded Processors

·        Verilog

 

Academic Honesty:           

Although it is fine to collaborate outside of class on all homework, laboratory, and exam questions, all work turned in for homework assignments and examinations is expected to represent individual solutions to the problems, and laboratory reports are expected to represent the work of the team named on the cover page. Having one person do a homework or lab assignment and another person simply duplicating the answers or report is considered cheating. Similarly, duplication of materials such as design, software, flow diagrams, or other documentation between laboratory teams is not acceptable. Copying another persons examinations papers, or working from someone else’s notes, or using material in addition to that allowed during an exam, is considered dishonest as well. Any acts of academic dishonesty will, at the least, result in immediate failure of the course for all individuals involved.

Copyright © 2002 to 2005 R. James Duckworth.

Developed and maintained by R. James Duckworth, rjduck@wpi.edu .