EE2022 B Term 2000

Homework - 3 (due start of class Monday November 20th)

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  1. [10 marks] Using switching algebra theorems simplify each of the following logic functions:

    2. (a) F = A.B + A.B.C’.D + A.B.D.E’ + A.B.C’.E + C’.D.E

    (b) F = M.N.O + Q’.P’.N’ + P.R.M + Q’O.M.P’ + M.R

  2. [10 marks] Write the truth table for each of the following logic functions:

    3. (a) F = A.B. + A.B’.C’ + A’.B.C

    (b) F = (A + A’).B + B.A.C’ + C.(A+B’).(A’+B)

  3. [10 marks] Write the canonical sum and product for each of the following logic functions:

    4. (a) F = S x,y(1,2)

    (b) F = P A,B(0,1,2)

    (c) F = S A,B,C(2,4,6,7)

    (d) F = P W,X,Y(0,1,3,4,5)

    (e) F = V’ + (W’.X’)’

  4. [20 marks] Using Karnaugh maps, find a minimal sum-of-products expression for each of the following logic functions.

    5. (a) F = S x,y,Z(1,3,5,6,7)

    (b) F = S w,x,y,Z(1,4,5,6,7,9,14,15)

    (c) F = P w,x,y(0,1,3,4,5)

    (d) F = S w,x,y,Z(0,2,5,7,8,10,13,15)

    (e) F = P A,B,c,D(0,1,7,9,13,15)

  5. [20 marks] Assume that you are to design part of an arithmetic unit in a microprocessor. The unit has to be able to add two 8-bit two’s complement numbers. Your part of the design is to produce a circuit to test if an overflow occurs. Your circuit should produce an output of a logic ‘1’ if overflow occurs and a logic ‘0’ otherwise.
  6. [20 marks] For the following circuit (see class):

 

(a) Write the algebraic expression for the function F in terms of the variables A, B, and C.

(b) Write the canonical sum and canonical product of the function F

(c) By algebraic manipulation minimize the circuit in sum of products form and implement the circuit with logic gates.

(d) Redesign the circuit from part (C) but this time use ONLY two-input NAND gates to implement the design.

(e) For the original circuit use a Karnaugh map to produce a simplified implementation.
  1. [10 marks] For the circuit from Q6 find the minimum and maximum propagation delays from input A to output F as input A changes from a logic '0' to a logic '1'. Assume inputs B and C stay at logic '1'. [Also assume CL = 15pF in your calculations]. Draw a timing diagram showing the logic levels changing from A to F.