Dr. R. James
Duckworth, AK301, Tel: (508) 831-5204, email: rjduck@wpi.edu
Office Hours: Thursday afternoon 2.00 to 4.0. Additional times by appointment (send email).
TA: Chen Shen: chen_shen@wpi.edu
Chen is
available everyday in AK209 from 2 to 5pm.
14 lectures (In AK233, 6.00 pm) starting Thursday September 10th and ending December 17th
(No class November 26 – Thanksgiving holiday)
Project presentations for final project – December 10th
Final exam and final project reports due December 17th
This is an introductory course on Verilog and
VHDL, two standard hardware description languages (HDLs), for students with no
background or prior experience with HDLs. In this course we will examine some
of the important features of Verilog and VHDL. The course will enable students
to design, simulate, model and synthesize digital designs. The dataflow,
structural, and behavioral modeling techniques will be discussed and related to
how they are used to design combinational and sequential circuits. The use of
test benches to exercise and verify the correctness of hardware models will
also be described.
Course Projects: Course projects will
involve the modeling and synthesis and testing using Xilinx tools. We will be
targeting Xilinx FPGA and CPLDs. Students will need to purchase the NEXSYS-2
FPGA development board for project assignments. (Other synthesis and simulation
tools may be used if these are available to the students at their place of
employment.) Students will have the choice of completing assignments in either
Verilog or VHDL.
Prerequisites: Logic Circuits and
experience with programming in a high-level language (such as C or Pascal) and
a computer architecture course such as ECE505.
Grading: The final grade is based ont he grades for the exam and lab reports. The weight for each part is:
· Final exam - 30%
· initial design project – (VGA Display with Serial Interface) 15% (report due by week 7)
· middle design project – (DSP Project) 15% (report and signoff due by week 11)
· final design project - 40% (presentation week 13 and report due week 14)
· Grade A(90-100), B(80-89), C(70-79)
· No late work accepted
·
Assignments and reports
- updated with grading guidelines
·
Design of VGA Display with Serial Interface
o
See vga ref comp
design (bottom of page) http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,451&Prod=NEXYS2
o
You must first
register, and then download and install the WebPack
o
Manufacturer of
Spartan 3 Boards
·
Picoblaze Resources:
§
Select the Picoblaze
for the Spartan 3 and download the design files (includes examples)
§
Important: Download
and read the UG129 "Picoblaze 8-bit embedded microcontroller"
document
§
Select the pBlazeIDE
and download V3.6 of the assembler/simulator
o
Simple Picoblaze
example project files for Nexsys2 Board - uses LEDs, DIP switches, and UART
§
ece574_pico.vhd is the
top level file, ece574.psm is the assembler file, target is Nexsys2 board.
o
Simple Picoblaze example
project files for Spartan 3 Starter Board (older board – just for
reference) - uses LEDs, DIP switches, and UART
§
ece574_pico.vhd is the
top level file, ece574.psm is the assembler file, target is Spartan 3 Starter
board.
·
Nexsys2 Board
Tutorials:
o
Decoder
Tutorial – (for Xilinx synthesis and downloading to the Nexsys2 board)
o
Encoder
Synthesis and Simulation (updated to Xilinx 11.1 with Test Bench
introduction)
·
Spartan 3 Starter
Board Tutorials (older board – just for reference)
o
Spartan
3 Decoder Tutorial (For Xilinx synthesis to Spartan 3 board) – equivalent Verilog tutorial
§
Spartan 3 Demo Tutorial
– similar to Spartan 3 Decoder Tutorial but also shows how to program the PROM
o
Spartan
3 Counter Tutorial (For Xilinx synthesis to Spartan 3 board) – equivalent Verilog tutorial
o
Spartan 3E LCD files – read me (Use these files
to provide a 4 digit display on the Spartan 3E starter board)
o
Encoder
implementation and simulation (VHDL and Verilog)
·
VHDL FAQ (http://www.eda.org/comp.lang.vhdl/)
– very useful resource
·
Paper presented at MSE
2005 on Embedded
System Design with FPGAs using HDLs
·
Ten Simple Rules
to follow!
·
Module 3:
Concurrent Signal Assignment Statements
·
Module 4: The
Process Statement
·
Module 10: VHDL for Modeling
·
Verilog
Academic Honesty:
Although it is OK to discuss
outside of class on all homework, laboratory, and exam questions, all work
turned in for homework assignments and examinations is expected to represent
individual solutions to the problems, and laboratory reports are expected to
represent the work of the team named on the cover page. Having one person do a
homework or lab assignment and another person simply duplicating the answers or
report is considered cheating. Similarly, duplication of materials such as
design, software, flow diagrams, or other documentation between laboratory
teams, from past projects, or other sources is not acceptable. Similarly, it is
not acceptable to use ANY VHDL or Verilog code from outside sources (including
the Xilinx CORE generator) unless specifically mentioned in the lab
description. All VHDL or Verilog must be your own design. Copying another
persons examinations papers, or working from someone else’s notes, or using
material in addition to that allowed during an exam, is considered dishonest as
well. Any acts of academic dishonesty will, at the least, result in immediate
failure of the course for all individuals involved.
Copyright © 2009 R. James Duckworth.
Developed and maintained by R. James Duckworth, rjduck@wpi.edu.