ECE3810: Advanced Digital System Design

D Term 2009

3/19/09: A few updates:

· Lab1 deadline now during your lab session during the third week of class and now worth 20% of lab grade.

· Lab 2 deadline also a week later.

· Exam 1 now Tuesday March 31^st.

· See updated academic honesty: It is not acceptable to use ANY VHDL code from outside sources (including the Xilinx CORE generator) unless specifically mentioned in the lab description. All VHDL must be your own design.

Note: If you do not already have the NEXSYS-2 development board (containing the 500,000 gate Spartan 3E FPGA) from an earlier course then you will need to obtain this from the ECE shop for $115.

Lab 1: (20% of lab grade). Complete the counter and PROM tutorial and modify the counter so it counts at 10Hz and counts from your ECE mailbox number up to 9999 and then restart at your mailbox number. This lab is to be completed individually.

No lab report is required but you need to hand in your VHDL (with headers and comments) and demo and signoff your design by your lab session during the third week.

Lecturer.

Dr. R. James Duckworth, AK301, Tel: (508) 831-5204, email: rjduck@wpi.edu

Office hours: Mon, Tue, Thur, Fri: 10 to 11am.

Staff.

TAs: Chen Shen: chen_shen@wpi.edu and Feng Xu: xufeng@wpi.edu

Senior Tutor: Robyn Colopy rcolopy@wpi.edu

Help sessions: Monday 2pm and Thursday noon in AK 113

Lectures, Labs.

25 lectures (in AK219 at 11am) including three exams

Lab sessions: (in Ak113) Tuesday morning, Tuesday afternoon, and Wednesday morning

Note: You only need to go to lab sessions to get help or to have your projects signed off.

Course Description

This is an introductory course addressing the systematic design of advanced digital logic systems. The emphasis is on top-down design starting with high level models using VHDL as a tool for the design, synthesis, modeling, and testing of VLSI devices. The emphasis will be on understanding functional design, layout, floor planning, designing for speed and power objectives, and testing. Finally, the integration of tools and design methodologies will be addressed through a discussion of system on a chip (SOC) integration, methodologies, design for performance, and design for test/testing. Topics: 1. hardware description languages, VHDL, system modeling, synthesis, simulation and testing of digital circuits; 2. VLSI design tools, transistor level design and behavior, layout, routing, clocking and testing. 3. design integration to achieve specific SOC goals including architecture, planning and integration, and testing. Laboratory exercises: VHDL models of combinational and sequential circuits, synthesizing these models to programmable logic devices, simulating the design, test-benches, transistor level IC design, IC design methodologies, circuit extraction and modeling, and high level SOC design methodologies.
Recommended background: ECE 3801 and experience with programming in a high-level language such as C or Pascal.
Suggested background: ECE 3901 and ECE 3803.
Students may not receive credit for ECE 3810 if they have received credit for either ECE 3815 or ECE 3902..

Textbooks: Textbook: Introductory VHDL From Simulation to Synthesis by Sudhakar Yalamanchilli, Xilinx Design Series, Prentice Hall, ISBN 0-13-080982-9. Note: this textbook includes the Xilinx Student Edition of the Foundation Series Software but do NOT use this software, use the WebPack software instead.

Help Sessions: See TA and Senior Tutor help session above

Homework: There is no formal homework for the course but make sure you read the text book and online reference materials.

Lab Assignments: There will be four labs. Lab signoff and reports are expected by the stated deadline – no late work accepted.

Exams: 3 one-hour exams (Tuesday Mar 31^st, Friday April 17^th, and Tuesday May 5th) - subject to change

Grading: The final grade is based on the grades for the exams and lab writeups.

The weight for each part is: Exams 60%, Labs 40%. Grade A (> 90), B (80-90), C (70-80)

Course Syllabus

In EE3801 you learned about designing digital systems (combinational and sequential circuits) using schematics. This course concentrates on using a Hardware Description Language (VHDL) to describe and simulate and synthesize more complex digital systems.

Presentations

· Module 1: Introduction

· Module 2: VHDL Basics

· Module 3: Concurrent Signal Assignment Statements

· Module 4: The Process Statement

· Module 5: Sequential Logic

· Module 6: State Machines

· Module 7: Miscellaneous

· Module 8: Test Benches

· Module 9: VHDL for testing

· Module 10: VHDL for Modeling

· Embedded Processors

· Verilog

Useful Links and Files

· Lab assignments

o Lab 2 VGA ref design pdf and VGA VHDL source

o Lab 3

o Lab 4

· Xilinx website

· Xilinx Webpack

o You must first register, and then download and install the WebPack

· Digilent Website

o Manufacturer of Spartan 3 Boards

· Picoblaze Resources:

o Xilinx Pixoblaze

§ Select the Picoblaze for the Spartan 3 and download the design files (includes examples)

§ Important: Download and read the UG129 "Picoblaze 8-bit embedded microcontroller" document

o Mediatronix website

§ Select the pBlazeIDE and download V3.6 of the assembler/simulator

o Simple Picoblaze example project files for Nexsys2 Board - uses LEDs, DIP switches, and UART

§ ece574_pico.vhd is the top level file, ece574.psm is the assembler file, target is Nexsys2 board.

o Simple Picoblaze example project files for Nexsys2 Board - uses LEDs, DIP switches, and UART

§ ece574_pico.vhd is the top level file, ece574.psm is the assembler file, target is Nexsys2 board.

· Nexsys2 Board Tutorials:

o Decoder Tutorial – (for Xilinx synthesis and downloading to the Nexsys2 board)

o Counter Tutorial

o PROM Tutorial

o Encoder Synthesis and Simulation

· Spartan 3 Starter Board Tutorials – ONLY for reference for the older board

o Spartan 3 Decoder Tutorial (For Xilinx synthesis to Spartan 3 board) – equivalent Verilog tutorial

§ Spartan 3 Demo Tutorial – similar to Spartan 3 Decoder Tutorial but also shows how to program the PROM

o Spartan 3 Counter Tutorial (For Xilinx synthesis to Spartan 3 board) – equivalent Verilog tutorial

· VHDL FAQ (http://www.eda.org/comp.lang.vhdl/) – very useful resource

· Paper presented at MSE 2005 on Embedded System Design with FPGAs using HDLs

· Ten Simple Rules to follow!

Course Schedule D 2009 (subject to change)

Monday	Tuesday	Wednesday	Thursday	Friday
(Mar 16)
(Mar 23)
(Mar 30)	Lab 1 due Exam 1	Lab 1 due
(Apr 6)				Lab 2 due
(Apr 13)				Exam 2
Patriots Day			Project Pres Day	Lab 3 due
(Apr 27)
(May 4)	Final Exam	Lab 4 due

Academic Honesty:

Although it is fine to collaborate outside of class on all homework, laboratory, and exam questions, all work turned in for homework assignments and examinations is expected to represent individual solutions to the problems, and laboratory reports are expected to represent the work of the team named on the cover page. Having one person do a homework or lab assignment and another person simply duplicating the answers or report is considered cheating. Similarly, duplication of materials such as design, software, flow diagrams, or other documentation between laboratory teams is not acceptable. Similarly, it is not acceptable to use ANY VHDL or Verilog code from outside sources (including the Xilinx CORE generator) unless specifically mentioned in the lab description. All VHDL or Verilog must be your own design. Copying another persons examinations papers, or working from someone else’s notes, or using material in addition to that allowed during an exam, is considered dishonest as well. Any acts of academic dishonesty will, at the least, result in immediate failure of the course for all individuals involved.

Developed and maintained by R. James Duckworth, rjduck@wpi.edu .