by Carsten Poulsen (May 9, 2005), updated by Hauke Daempfling (July 1, 2005)
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This is a fast introduction on how to use the Xilinx EDK. The Xilinx EDK can work alone but if you want to integrate a component into a design, then you will also need the ISE.
It is recommended that you both install ISE and EDK and the latest service packs.
It is basically very simple. You start out by building your hardware platform:
1 - Build you hardware, add processors, busses etc.
2 - Generate a netlist (Takes some time)
3 - Generate a bitstream (Takes long time)
Then you add your applications that you want to run on your hardware:
4 - Design your software
5 - Compile it
6 - Merge it into the bitstream by updating the bitstream
Below are the screenshots of how to do this.
By right clicking in the System window you can add/edit hardware to your system.
As you can see it is possible to add/edit:
After you have designed your hardware, you generate a netlist. The netlist describes how everything is interconnected. This is similar to if you were designing a PCB from a schematic.
When you have created the netlist you can create the hardware part of the bitstream that will be downloaded to the FPGA.
And now to the software part...
By clicking the applications tab in the left side panel you get an overview of the software applications in your system. Here you can also find the location of your source code, headers, compiler settings etc.
Make sure that the software project you want to use is both marked as "active" and is "marked to initialize to BRAM"! To check this, right-click on the respective software project. When everything is OK, you build your applications by selecting "Build all user applications" in the Tools menu.
You have now made the part of the bitstream that contains your software code. You will therefore have to update the bitstream.
And finally you are ready to download the bitstream to the target, by using the USB JTAG cable.
Alternatively, you can use iMPACT to download the "download.bit" file in the "implementation" subdirectory of your project.
There is a compatibility problem with the MDM module in the XPS and the Virtex4. See Xilinx answer record 20060.
I have zipped a modified reference design project. Please refer to the Reference Design User Guide (UG082) for details. By downloading and unzipping this design you can avoid rebuilding the whole design from scratch, which takes some time. But do not change anything in it since this will force you to recreate the netlist and rebuild your bitstream.
When building the bitstream for the reference design there is an error because of a timing constraint defined in the UCF file in the project. I have changed this in the UCF file on line 439 in my modified reference design since I could not build the bitstream without doing so. This might lead to an error somewhere.
# TIMESPEC "TSRXIN" = FROM "PADS" TO "RXCLK_GRP" 6.25 ns;
TIMESPEC "TSRXIN" = FROM "PADS" TO "RXCLK_GRP" 15.00 ns;
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