2002 to 2007: Ph.D. in Computer Engineering, Worcester
Polytechnic Institute, Massachusetts, U.S.A.
2000 to 2002: M.S. in Electrical Engineering, Worcester Polytechnic
Institute,
Massachusetts, U.S.A.
1995 to 2000: Dipl.-Ing. (FH) in Electrical Engineering, Munich
University of Applied
Sciences, Germany
Research Interests
Cryptography
Computer Arithmetic
Fault Tolerance
Coding Theory
VLSI Design (Low-Power Arithmetic Circuits, Asynchronous
Digital
Circuits)
Network Processors
Publications
B. Sunar, G. Gaubatz and C. Paar. A Strong Method for Error Detection in Optimal Extension Field Arithmetic. Submitted for review.
E. Öztürk, G. Gaubatz and B. Sunar. Tate Pairing with Strong Fault Resiliency. Accepted to the 3rd Workshop on Fault Diagnosis and Tolerance in Cryptography 2007 (FDTC'07), Vienna, Austria, September 2007.
G. Gaubatz. Tamper-Resistant Arithmetic for Public-Key Cryptography. Ph.D. Dissertation, Worcester Polytechnic Institute, Massachusetts, May 2007.
W. C. Hasenplaugh, V. Gopal and G. Gaubatz. Fast
Modular Reduction. Accepted to the 18th IEEE Symposium on
Computer Arithmetic in Montpellier, France, July 2007.