|
Deniz Karakoyunlu
PhD Student Cryptography & Information Security Laboratory Electrical and Computer Engineering Department Worcester Polytechnic Institute 100 Institute Road, Worcester, MA 01609-2280 Ph: (508) 831-5840
RESEARCH INTERESTS· Cryptographic Hardware Design · Computer Architecture and Arithmetic · VLSI Design DEGREES· February, 2007 : MSc in Electrical and Computer Engineering, Worcester Polytechnic Institute, Worcester, MA, USA · July, 2004 : BSc in Microelectronics Engineering, Sabanci University, Istanbul, Turkey PUBLICATIONS· V. Gopal, E. Ozturk, J. Guilford, G. Wolrich, W. Feghali, M. Dixon, D. Karakoyunlu. “Fast CRC Computation for Generic Polynomials Using PCLMULQDQ Instruction”. Intel White Paper, 2009. · S. K. Yoo, D. Karakoyunlu, B. Birand, B. Sunar. “Improving the Robustness of Ring Oscillator TRNGs”. To appear in ACM Transactions on Reconfigurable Technology and Systems Journal, 2010. · D. Karakoyunlu, F. K. Gurkaynak, B. Sunar, Y. Leblebici. “Efficient and Side-Channel-Aware Implementations of Elliptic Curve Cryptosystems over Prime Fields”. IET Information Security, Volume 4, Issue 1, Pages: 30-43, 2010. · D. Agrawal, S. Baktir, D. Karakoyunlu, P. Rohatgi, B. Sunar. “Trojan Detection using IC Fingerprinting”. Proceedings of the 2007 IEEE Symposium on Security and Privacy, Oakland, CA, USA, 2007. · D. Agrawal, S. Baktir, D. Karakoyunlu, P. Rohatgi, B. Sunar. “Trojan Detection using IC Fingerprinting”. IBM Research Report, RC24110, 2006. AWARDS· Spontaneous Recognition Award, Intel (May 2009) · IBM, 2007 Pat Goldberg Memorial Best Paper Award, IBM Research (July 2008) · Division Recognition Award, Intel (Q3 2008) · Best Poster Presentation Award, WPI - ECE Department (PhD Category - First Place, April 2008; PhD Category - Third Place, April 2006) WORK EXPERIENCE· Graduate Intern Technical, Intel Massachusetts, Hudson, MA (May - August 2009, May - August 2008) Analyzed performance of various cryptographic/content-processing algorithms (such as AES, CRC, GHASH and GCM-ESP) by development and simulation of assembly routines on the most recent Intel Architecture (IA), and developed performance optimizations using the latest research and efficient implementation techniques. Developed an optimized version of CRC algorithm, and integrated this method in GZIP compression code along with optimizations in the compression algorithm. · Co-op Engineer, AMD Boston Design Center, Boxborough, MA (May - August 2006, May - December 2005) Contributed to the verification of Fully Buffered Dual Inline Memory Module Physical Layer (FBDIMM-PHY) by building register transfer level (RTL) models, verifying the components of the module via RTL and Spice simulations, cooperating with design architects to suggest algorithmic enhancements to the design, and updating legacy tests developed for a previous version of the memory controller. Validated Spice netlist and RTL netlist of the complete module for equivalency by running Cadence Conformal Logic Equivalence Checker, which was unprecedented at AMD. · Intern, Nortel Networks NETAS, Istanbul, Turkey (May - August 2003) Collaborated in Hardware Research and Development Team by implementing Java Optimized Processor and Ethernet intellectual property core on a single Field Programmable Gate Array (FPGA) Chip to obtain an intelligent Ethernet topology that removes the central processing unit from the communication burden. Developed glue logic for two modules, and evaluated various test cases to verify the correct operation of the combined module after understanding the Ethernet protocol and instruction set of the Java Optimized Processor. · Intern, Derece Software Services, Izmir, Turkey (June - August 2002) Developed the core Microsoft object linking and embedding (OLE) control extension for a software system assisting milk production companies in commerce and accounting operations. Built a graphical user interface for efficient interaction between the user and the software. RESEARCH EXPERIENCE· WPI, Electrical and Computer Engineering Department, Worcester, MA, USA (August 2004 - Present) PhD Thesis: Side-Channel Resilient Elliptic Curve Cryptosystems Presented a comprehensive overview and comparison of Elliptic Curve Cryptosystems (ECC) over finite fields of prime characteristics using both affine and projective coordinates, and utilizing conventional Weierstrass formulations and recently introduced Edwards formulations that are promising in performance with built-in resiliency against simple side-channel attacks. Introduced a side channel aware version of non-adjacent form (NAF) scalar multiplication algorithm for Edwards formulation. · Swiss Federal Institute of Technology, Lausanne, Switzerland (June - December 2007) Visiting Researcher Realized an application specific integrated circuit (ASIC) implementation of efficient and side channel aware elliptic curve cryptosystems (ECC) by writing up the requirements, selecting appropriate algorithms for improving the performance at various implementation levels without undermining side channel awareness, developing the hardware description language (HDL) implementations of these algorithms, and performing the placement and routing of the silicon chip. · WPI, Electrical and Computer Engineering Department, Worcester, MA, USA (January - May 2006) Research Assistant in collaboration with IBM T.J. Watson Research Center Proposed a novel methodology for detecting malicious modification of the integrated circuitries using side channel analysis techniques. Built a custom RSA public key cryptographic core for establishing the validity of IC fingerprinting approach with power simulation and power trace analysis. |
