-------------------------------------------------------------------------------
-- opb_uart16550_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

library UNISIM;
use UNISIM.VCOMPONENTS.ALL;

library proc_utils_v1_00_a;
use proc_utils_v1_00_a.all;

library proc_common_v1_00_a;
use proc_common_v1_00_a.all;

library lib_common_v1_00_a;
use lib_common_v1_00_a.all;

library opb_ipif_v1_23_a;
use opb_ipif_v1_23_a.all;

library opb_uart16550_v1_00_c;
use opb_uart16550_v1_00_c.all;

entity opb_uart16550_0_wrapper is
  port (
    OPB_Clk : in std_logic;
    OPB_Rst : in std_logic;
    IP2INTC_Irpt : out std_logic;
    Freeze : in std_logic;
    OPB_ABus : in std_logic_vector(0 to 31);
    OPB_BE : in std_logic_vector(0 to 3);
    OPB_RNW : in std_logic;
    OPB_select : in std_logic;
    OPB_seqAddr : in std_logic;
    OPB_DBus : in std_logic_vector(0 to 31);
    Sln_DBus : out std_logic_vector(0 to 31);
    Sln_ErrAck : out std_logic;
    Sln_Retry : out std_logic;
    Sln_ToutSup : out std_logic;
    Sln_XferAck : out std_logic;
    baudoutN : out std_logic;
    ctsN : in std_logic;
    dcdN : in std_logic;
    ddis : out std_logic;
    dsrN : in std_logic;
    dtrN : out std_logic;
    out1N : out std_logic;
    out2N : out std_logic;
    rclk : in std_logic;
    riN : in std_logic;
    rtsN : out std_logic;
    rxrdyN : out std_logic;
    sin : in std_logic;
    sout : out std_logic;
    txrdyN : out std_logic;
    xin : in std_logic;
    xout : out std_logic
  );
  attribute x_core_info : STRING;
  attribute x_core_info of opb_uart16550_0_wrapper: entity is "opb_uart16550_v1_00_c";

end opb_uart16550_0_wrapper;

architecture STRUCTURE of opb_uart16550_0_wrapper is

  component opb_uart16550 is
    generic (
      C_BASEADDR : std_logic_vector;
      C_HIGHADDR : std_logic_vector;
      C_DEV_BLK_ID : integer;
      C_IS_A_16550 : integer;
      C_HAS_EXTERNAL_XIN : integer;
      C_HAS_EXTERNAL_RCLK : integer;
      C_OPB_AWIDTH : integer;
      C_OPB_DWIDTH : integer;
      C_DEV_MIR_ENABLE : integer
    );
    port (
      OPB_Clk : in std_logic;
      OPB_Rst : in std_logic;
      IP2INTC_Irpt : out std_logic;
      Freeze : in std_logic;
      OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1);
      OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1);
      OPB_RNW : in std_logic;
      OPB_select : in std_logic;
      OPB_seqAddr : in std_logic;
      OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1);
      Sln_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);
      Sln_ErrAck : out std_logic;
      Sln_Retry : out std_logic;
      Sln_ToutSup : out std_logic;
      Sln_XferAck : out std_logic;
      baudoutN : out std_logic;
      ctsN : in std_logic;
      dcdN : in std_logic;
      ddis : out std_logic;
      dsrN : in std_logic;
      dtrN : out std_logic;
      out1N : out std_logic;
      out2N : out std_logic;
      rclk : in std_logic;
      riN : in std_logic;
      rtsN : out std_logic;
      rxrdyN : out std_logic;
      sin : in std_logic;
      sout : out std_logic;
      txrdyN : out std_logic;
      xin : in std_logic;
      xout : out std_logic
    );
  end component;

begin

  opb_uart16550_0 : opb_uart16550
    generic map (
      C_BASEADDR => X"a0000000",
      C_HIGHADDR => X"a0001FFF",
      C_DEV_BLK_ID => 0,
      C_IS_A_16550 => 1,
      C_HAS_EXTERNAL_XIN => 0,
      C_HAS_EXTERNAL_RCLK => 0,
      C_OPB_AWIDTH => 32,
      C_OPB_DWIDTH => 32,
      C_DEV_MIR_ENABLE => 0
    )
    port map (
      OPB_Clk => OPB_Clk,
      OPB_Rst => OPB_Rst,
      IP2INTC_Irpt => IP2INTC_Irpt,
      Freeze => Freeze,
      OPB_ABus => OPB_ABus,
      OPB_BE => OPB_BE,
      OPB_RNW => OPB_RNW,
      OPB_select => OPB_select,
      OPB_seqAddr => OPB_seqAddr,
      OPB_DBus => OPB_DBus,
      Sln_DBus => Sln_DBus,
      Sln_ErrAck => Sln_ErrAck,
      Sln_Retry => Sln_Retry,
      Sln_ToutSup => Sln_ToutSup,
      Sln_XferAck => Sln_XferAck,
      baudoutN => baudoutN,
      ctsN => ctsN,
      dcdN => dcdN,
      ddis => ddis,
      dsrN => dsrN,
      dtrN => dtrN,
      out1N => out1N,
      out2N => out2N,
      rclk => rclk,
      riN => riN,
      rtsN => rtsN,
      rxrdyN => rxrdyN,
      sin => sin,
      sout => sout,
      txrdyN => txrdyN,
      xin => xin,
      xout => xout
    );

end architecture STRUCTURE;

