-------------------------------------------------------------------------------
-- opb_iic_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

library UNISIM;
use UNISIM.VCOMPONENTS.ALL;

library lib_common_v1_00_a;
use lib_common_v1_00_a.all;

library proc_common_v1_00_a;
use proc_common_v1_00_a.all;

library proc_utils_v1_00_a;
use proc_utils_v1_00_a.all;

library opb_ipif_v1_23_a;
use opb_ipif_v1_23_a.all;

library opb_iic_v1_01_c;
use opb_iic_v1_01_c.all;

entity opb_iic_0_wrapper is
  port (
    OPB_Clk : in std_logic;
    Sda_I : in std_logic;
    Sda_O : out std_logic;
    Sda_T : out std_logic;
    Scl_I : in std_logic;
    Scl_O : out std_logic;
    Scl_T : out std_logic;
    Gpo : out std_logic_vector(31 to 31);
    OPB_ABus : in std_logic_vector(0 to 31);
    OPB_DBus : in std_logic_vector(0 to 31);
    Sln_DBus : out std_logic_vector(0 to 31);
    OPB_select : in std_logic;
    OPB_RNW : in std_logic;
    Sln_xferAck : out std_logic;
    Sln_errAck : out std_logic;
    Sln_toutSup : out std_logic;
    Sln_retry : out std_logic;
    IP2INTC_Irpt : out std_logic;
    OPB_Rst : in std_logic;
    Freeze : in std_logic;
    OPB_seqAddr : in std_logic;
    OPB_BE : in std_logic_vector(0 to 3)
  );
  attribute x_core_info : STRING;
  attribute x_core_info of opb_iic_0_wrapper: entity is "opb_iic_v1_01_c";

end opb_iic_0_wrapper;

architecture STRUCTURE of opb_iic_0_wrapper is

  component opb_iic is
    generic (
      C_CLK_FREQ : INTEGER;
      C_IIC_FREQ : INTEGER;
      C_TEN_BIT_ADR : INTEGER;
      C_GPO_WIDTH : INTEGER;
      C_DEV_BLK_ID : INTEGER;
      C_DEV_MIR_ENABLE : INTEGER;
      C_BASEADDR : std_logic_vector;
      C_HIGHADDR : std_logic_vector;
      C_OPB_AWIDTH : INTEGER;
      C_OPB_DWIDTH : INTEGER
    );
    port (
      OPB_Clk : in std_logic;
      Sda_I : in std_logic;
      Sda_O : out std_logic;
      Sda_T : out std_logic;
      Scl_I : in std_logic;
      Scl_O : out std_logic;
      Scl_T : out std_logic;
      Gpo : out std_logic_vector((32-C_GPO_WIDTH) to (C_OPB_DWIDTH-1));
      OPB_ABus : in std_logic_vector(0 to (C_OPB_AWIDTH-1));
      OPB_DBus : in std_logic_vector(0 to (C_OPB_DWIDTH-1));
      Sln_DBus : out std_logic_vector(0 to (C_OPB_DWIDTH-1));
      OPB_select : in std_logic;
      OPB_RNW : in std_logic;
      Sln_xferAck : out std_logic;
      Sln_errAck : out std_logic;
      Sln_toutSup : out std_logic;
      Sln_retry : out std_logic;
      IP2INTC_Irpt : out std_logic;
      OPB_Rst : in std_logic;
      Freeze : in std_logic;
      OPB_seqAddr : in std_logic;
      OPB_BE : in std_logic_vector(0 to ((C_OPB_DWIDTH/8)-1))
    );
  end component;

begin

  opb_iic_0 : opb_iic
    generic map (
      C_CLK_FREQ => 100000000,
      C_IIC_FREQ => 100000,
      C_TEN_BIT_ADR => 0,
      C_GPO_WIDTH => 1,
      C_DEV_BLK_ID => 0,
      C_DEV_MIR_ENABLE => 0,
      C_BASEADDR => X"A8000000",
      C_HIGHADDR => X"A80001FF",
      C_OPB_AWIDTH => 32,
      C_OPB_DWIDTH => 32
    )
    port map (
      OPB_Clk => OPB_Clk,
      Sda_I => Sda_I,
      Sda_O => Sda_O,
      Sda_T => Sda_T,
      Scl_I => Scl_I,
      Scl_O => Scl_O,
      Scl_T => Scl_T,
      Gpo => Gpo,
      OPB_ABus => OPB_ABus,
      OPB_DBus => OPB_DBus,
      Sln_DBus => Sln_DBus,
      OPB_select => OPB_select,
      OPB_RNW => OPB_RNW,
      Sln_xferAck => Sln_xferAck,
      Sln_errAck => Sln_errAck,
      Sln_toutSup => Sln_toutSup,
      Sln_retry => Sln_retry,
      IP2INTC_Irpt => IP2INTC_Irpt,
      OPB_Rst => OPB_Rst,
      Freeze => Freeze,
      OPB_seqAddr => OPB_seqAddr,
      OPB_BE => OPB_BE
    );

end architecture STRUCTURE;

