-------------------------------------------------------------------------------
-- opb_ethernet_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

library UNISIM;
use UNISIM.VCOMPONENTS.ALL;

library proc_common_v1_00_b;
use proc_common_v1_00_b.all;

library lib_common_v1_00_a;
use lib_common_v1_00_a.all;

library ipif_common_v1_00_d;
use ipif_common_v1_00_d.all;

library opb_ipif_v2_00_h;
use opb_ipif_v2_00_h.all;

library opb_ethernet_v1_01_a;
use opb_ethernet_v1_01_a.all;

entity opb_ethernet_0_wrapper is
  port (
    PHY_tx_clk : in std_logic;
    PHY_rx_clk : in std_logic;
    PHY_crs : in std_logic;
    PHY_dv : in std_logic;
    PHY_rx_data : in std_logic_vector(3 downto 0);
    PHY_col : in std_logic;
    PHY_rx_er : in std_logic;
    OPB_ABus : in std_logic_vector(0 to 31);
    OPB_DBus : in std_logic_vector(0 to 31);
    OPB_errAck : in std_logic;
    OPB_BE : in std_logic_vector(0 to 3);
    OPB_MGrant : in std_logic;
    OPB_retry : in std_logic;
    OPB_RNW : in std_logic;
    OPB_select : in std_logic;
    OPB_seqAddr : in std_logic;
    OPB_timeout : in std_logic;
    OPB_xferAck : in std_logic;
    Freeze : in std_logic;
    OPB_Clk : in std_logic;
    OPB_Rst : in std_logic;
    PHY_tx_en : out std_logic;
    PHY_rx_en : out std_logic;
    PHY_tx_er : out std_logic;
    PHY_tx_data : out std_logic_vector(3 downto 0);
    PHY_rst_n : out std_logic;
    Sln_xferAck : out std_logic;
    Sln_errAck : out std_logic;
    Sln_retry : out std_logic;
    Sln_toutSup : out std_logic;
    Sln_DBus : out std_logic_vector(0 to 31);
    Mn_request : out std_logic;
    Mn_busLock : out std_logic;
    Mn_select : out std_logic;
    Mn_RNW : out std_logic;
    Mn_BE : out std_logic_vector(0 to 3);
    Mn_seqAddr : out std_logic;
    Mn_ABus : out std_logic_vector(0 to 31);
    emac_intrpts : out std_logic_vector(0 to 21);
    IP2INTC_Irpt : out std_logic;
    PHY_Mii_clk_I : in std_logic;
    PHY_Mii_clk_O : out std_logic;
    PHY_Mii_clk_T : out std_logic;
    PHY_Mii_data_I : in std_logic;
    PHY_Mii_data_O : out std_logic;
    PHY_Mii_data_T : out std_logic
  );
  attribute x_core_info : STRING;
  attribute x_core_info of opb_ethernet_0_wrapper: entity is "opb_ethernet_v1_01_a";

end opb_ethernet_0_wrapper;

architecture STRUCTURE of opb_ethernet_0_wrapper is

  component opb_ethernet is
    generic (
      C_DEV_BLK_ID : INTEGER;
      C_DEV_MIR_ENABLE : INTEGER;
      C_BASEADDR : std_logic_vector;
      C_HIGHADDR : std_logic_vector;
      C_RESET_PRESENT : INTEGER;
      C_INCLUDE_DEV_PENCODER : INTEGER;
      C_DMA_PRESENT : INTEGER;
      C_DMA_INTR_COALESCE : INTEGER;
      C_OPB_AWIDTH : INTEGER;
      C_OPB_DWIDTH : INTEGER;
      C_OPB_CLK_PERIOD_PS : INTEGER;
      C_FAMILY : STRING;
      C_IPIF_FIFO_DEPTH : INTEGER;
      C_MIIM_CLKDVD : std_logic_vector;
      C_SOURCE_ADDR_INSERT_EXIST : INTEGER;
      C_PAD_INSERT_EXIST : INTEGER;
      C_FCS_INSERT_EXIST : INTEGER;
      C_MAC_FIFO_DEPTH : INTEGER;
      C_HALF_DUPLEX_EXIST : INTEGER;
      C_ERR_COUNT_EXIST : INTEGER;
      C_MII_EXIST : INTEGER
    );
    port (
      PHY_tx_clk : in std_logic;
      PHY_rx_clk : in std_logic;
      PHY_crs : in std_logic;
      PHY_dv : in std_logic;
      PHY_rx_data : in std_logic_vector(3 downto 0);
      PHY_col : in std_logic;
      PHY_rx_er : in std_logic;
      OPB_ABus : in std_logic_vector(0 to (C_OPB_AWIDTH-1));
      OPB_DBus : in std_logic_vector(0 to (C_OPB_DWIDTH-1));
      OPB_errAck : in std_logic;
      OPB_BE : in std_logic_vector(0 to (4-1));
      OPB_MGrant : in std_logic;
      OPB_retry : in std_logic;
      OPB_RNW : in std_logic;
      OPB_select : in std_logic;
      OPB_seqAddr : in std_logic;
      OPB_timeout : in std_logic;
      OPB_xferAck : in std_logic;
      Freeze : in std_logic;
      OPB_Clk : in std_logic;
      OPB_Rst : in std_logic;
      PHY_tx_en : out std_logic;
      PHY_rx_en : out std_logic;
      PHY_tx_er : out std_logic;
      PHY_tx_data : out std_logic_vector(3 downto 0);
      PHY_rst_n : out std_logic;
      Sln_xferAck : out std_logic;
      Sln_errAck : out std_logic;
      Sln_retry : out std_logic;
      Sln_toutSup : out std_logic;
      Sln_DBus : out std_logic_vector(0 to (C_OPB_DWIDTH-1));
      Mn_request : out std_logic;
      Mn_busLock : out std_logic;
      Mn_select : out std_logic;
      Mn_RNW : out std_logic;
      Mn_BE : out std_logic_vector(0 to (4-1));
      Mn_seqAddr : out std_logic;
      Mn_ABus : out std_logic_vector(0 to (C_OPB_AWIDTH-1));
      emac_intrpts : out std_logic_vector(0 to 21);
      IP2INTC_Irpt : out std_logic;
      PHY_Mii_clk_I : in std_logic;
      PHY_Mii_clk_O : out std_logic;
      PHY_Mii_clk_T : out std_logic;
      PHY_Mii_data_I : in std_logic;
      PHY_Mii_data_O : out std_logic;
      PHY_Mii_data_T : out std_logic
    );
  end component;

begin

  opb_ethernet_0 : opb_ethernet
    generic map (
      C_DEV_BLK_ID => 0,
      C_DEV_MIR_ENABLE => 1,
      C_BASEADDR => X"60000000",
      C_HIGHADDR => X"60003FFF",
      C_RESET_PRESENT => 1,
      C_INCLUDE_DEV_PENCODER => 1,
      C_DMA_PRESENT => 1,
      C_DMA_INTR_COALESCE => 1,
      C_OPB_AWIDTH => 32,
      C_OPB_DWIDTH => 32,
      C_OPB_CLK_PERIOD_PS => 10000,
      C_FAMILY => "virtex4",
      C_IPIF_FIFO_DEPTH => 65536,
      C_MIIM_CLKDVD => B"11111",
      C_SOURCE_ADDR_INSERT_EXIST => 1,
      C_PAD_INSERT_EXIST => 1,
      C_FCS_INSERT_EXIST => 1,
      C_MAC_FIFO_DEPTH => 64,
      C_HALF_DUPLEX_EXIST => 1,
      C_ERR_COUNT_EXIST => 1,
      C_MII_EXIST => 1
    )
    port map (
      PHY_tx_clk => PHY_tx_clk,
      PHY_rx_clk => PHY_rx_clk,
      PHY_crs => PHY_crs,
      PHY_dv => PHY_dv,
      PHY_rx_data => PHY_rx_data,
      PHY_col => PHY_col,
      PHY_rx_er => PHY_rx_er,
      OPB_ABus => OPB_ABus,
      OPB_DBus => OPB_DBus,
      OPB_errAck => OPB_errAck,
      OPB_BE => OPB_BE,
      OPB_MGrant => OPB_MGrant,
      OPB_retry => OPB_retry,
      OPB_RNW => OPB_RNW,
      OPB_select => OPB_select,
      OPB_seqAddr => OPB_seqAddr,
      OPB_timeout => OPB_timeout,
      OPB_xferAck => OPB_xferAck,
      Freeze => Freeze,
      OPB_Clk => OPB_Clk,
      OPB_Rst => OPB_Rst,
      PHY_tx_en => PHY_tx_en,
      PHY_rx_en => PHY_rx_en,
      PHY_tx_er => PHY_tx_er,
      PHY_tx_data => PHY_tx_data,
      PHY_rst_n => PHY_rst_n,
      Sln_xferAck => Sln_xferAck,
      Sln_errAck => Sln_errAck,
      Sln_retry => Sln_retry,
      Sln_toutSup => Sln_toutSup,
      Sln_DBus => Sln_DBus,
      Mn_request => Mn_request,
      Mn_busLock => Mn_busLock,
      Mn_select => Mn_select,
      Mn_RNW => Mn_RNW,
      Mn_BE => Mn_BE,
      Mn_seqAddr => Mn_seqAddr,
      Mn_ABus => Mn_ABus,
      emac_intrpts => emac_intrpts,
      IP2INTC_Irpt => IP2INTC_Irpt,
      PHY_Mii_clk_I => PHY_Mii_clk_I,
      PHY_Mii_clk_O => PHY_Mii_clk_O,
      PHY_Mii_clk_T => PHY_Mii_clk_T,
      PHY_Mii_data_I => PHY_Mii_data_I,
      PHY_Mii_data_O => PHY_Mii_data_O,
      PHY_Mii_data_T => PHY_Mii_data_T
    );

end architecture STRUCTURE;

