-------------------------------------------------------------------------------
-- opb_sysace.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
--  ***************************************************************************
--  **  Copyright(C) 2003 by Xilinx, Inc. All rights reserved.               **
--  **                                                                       **
--  **  This text contains proprietary, confidential                         **
--  **  information of Xilinx, Inc. , is distributed by                      **
--  **  under license from Xilinx, Inc., and may be used,                    **
--  **  copied and/or disclosed only pursuant to the terms                   **
--  **  of a valid license agreement with Xilinx, Inc.                       **
--  **                                                                       **
--  **  Unmodified source code is guaranteed to place and route,             **
--  **  function and run at speed according to the datasheet                 **
--  **  specification. Source code is provided "as-is", with no              **
--  **  obligation on the part of Xilinx to provide support.                 **
--  **                                                                       **
--  **  Xilinx Hotline support of source code IP shall only include          **
--  **  standard level Xilinx Hotline support, and will only address         **
--  **  issues and questions related to the standard released Netlist        **
--  **  version of the core (and thus indirectly, the original core source). **
--  **                                                                       **
--  **  The Xilinx Support Hotline does not have access to source            **
--  **  code and therefore cannot answer specific questions related          **
--  **  to source HDL. The Xilinx Support Hotline will only be able          **
--  **  to confirm the problem in the Netlist version of the core.           **
--  **                                                                       **
--  **  This copyright and support notice must be retained as part           **
--  **  of this text at all times.                                           **
--  ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename:        opb_sysace.vhd
-- Version:         v1.00b
-- Description:     This is the top-level design file for the SystemACE 
--                  Controller.
--
-- VHDL-Standard:   VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--                  opb_sysace.vhd
--                      -- opb_ipif.vhd
--                      -- sysace.vhd
--                          --mem_state_machine.vhd
--                          -- sync_2_clock.vhd
--
-------------------------------------------------------------------------------
-- @BEGIN_CHANGELOG EDK_Gm_SP2
-- Corrected value for MIN_SIZE attribute from 0x7F to 0x80. Added attributes
-- as shown below:
--
--      Attribute           Applied to Generics
--      ----------          --------------------
--      ASSIGNMENT          C_BASEADDR, C_HIGHADDR, C_OPB_DWIDTH, C_OPB_AWIDTH
--      XRANGE              C_MEM_WIDTH
--
-- @END_CHANGELOG
-------------------------------------------------------------------------------
-- Author:      DAB
-- History:
--  DAB      09-19-2002      -- First version
--
-- DAB      10-18-2002       -- Remove Wait State Generator and all associated 
--                              Logic
-- DAB      10-25-2002       -- Removed C_OPB_CLK_PERIOD_PS and added interrupt
-- ALS      08-25-2003  
-- ~~~~~~
-- Moved to OPB IPIF V3, reduced pipelined registers, removed XST workaround,
-- and fixed data capture
-- ^^^^^^
-- ALS      04/25/04
-- ^^^^^^
-- Corrected MIN_SIZE attribute, added ASSIGNMENT and XRANGE attributes,
-- and added CHANGE LOG.
-- ~~~~~~
-------------------------------------------------------------------------------

-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "clk_div#", "clk_#x"
--      reset signals:                          "rst", "rst_n"
--      generics:                               "C_*"
--      user defined types:                     "*_TYPE"
--      state machine next state:               "*_ns"
--      state machine current state:            "*_cs"
--      combinatorial signals:                  "*_cmb"
--      pipelined or register delay signals:    "*_d#"
--      counter signals:                        "*cnt*"
--      clock enable signals:                   "*_ce"
--      internal version of output port         "*_i"
--      device pins:                            "*_pin"
--      ports:                                  - Names begin with Uppercase
--      processes:                              "*_PROCESS"
--      component instantiations:               "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.conv_std_logic_vector;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
use IEEE.std_logic_misc.all;

library unisim;
use unisim.vcomponents.all;

library proc_common_v1_00_b;
use proc_common_v1_00_b.proc_common_pkg.all;
use proc_common_v1_00_b.all;

library ipif_common_v1_00_c;
use ipif_common_v1_00_c.ipif_pkg.all;
use ipif_common_v1_00_c.all;

library opb_ipif_v3_00_a;
use opb_ipif_v3_00_a.all;

library sysace_common_v1_00_b;
use sysace_common_v1_00_b.all;

--
-- library unsigned is used for overloading of "=" which allows integer to
-- be compared to std_logic_vector
use ieee.std_logic_unsigned.all;
--
-------------------------------------------------------------------------------
-- Definition of Generics:
--  C_BASEADDR                      --  Base address for SYSACE
--  C_HIGHADDR                      --  High address for SYSACE
--  C_MEM_WIDTH                     --  Data width of SYSACE
--  C_OPB_DWIDTH                    --  OPB Data Bus Width
--  C_OPB_AWIDTH                    --  OPB Address Width
--
-- Definition of Ports:
-- OPB Interface
--  OPB_Clk                         -- OPB clock                                               
--  OPB_Rst                         -- OPB Reset                                               
--  OPB_ABus                        -- OPB address bus                                             
--  OPB_DBus                        -- OPB data bus                                                   
--  Sln_DBus                        -- Slave read bus                                         
--  OPB_select                      -- OPB select                                    
--  OPB_RNW                         -- OPB read not write                                           
--  OPB_seqAddr                     -- OPB sequential address                              
--  OPB_BE                          -- OPB byte enables                                              
--  Sln_xferAck                     -- Slave transfer acknowledge                            
--  Sln_errAck                      -- Slave error acknowledge
--  Sln_toutSup                     -- Slave timeout suppress
--  Sln_retry                       -- Slave retry
--
--    -- Memory signals
--  SysACE_MPA                      -- SYSACE address inputs
--  SysACE_CLK                      -- SYSACE clock
--  SysACE_MPIRQ                    -- SYSACE interrupt
--  SysACE_MPD_I                    -- SYSACE input data bus
--  SysACE_MPD_O                    -- SYSACE output data bus
--  SysACE_MPD_T                    -- SYSACE data output enable
--  SysACE_CEN                      -- SYSACE chip select
--  SysACE_OEN                      -- SYSACE output enable
--  SysACE_WEN                      -- SYSACE write enable
--  SysACE_IRQ                      -- SYSACE interrupt

-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------

entity opb_sysace is
   -- Generics to be set by user
  generic (
    C_BASEADDR                      : std_logic_vector := X"FFFFFFFF";
    C_HIGHADDR                      : std_logic_vector := X"00000000";
    C_MEM_WIDTH                     : integer := 16;
    --Generics set for OPB
    C_OPB_DWIDTH                    : integer := 32;
    C_OPB_AWIDTH                    : integer := 32
    
        );
  port
      (
       -- System Port Declarations ********************************************

       OPB_Clk         :   in std_logic;
       OPB_Rst         :   in std_logic;

       -- OPB Port Declarations ***********************************************
       OPB_ABus       : in std_logic_vector(0 to C_OPB_AWIDTH - 1 );
       OPB_DBus       : in std_logic_vector(0 to C_OPB_DWIDTH - 1 );
       Sln_DBus       : out std_logic_vector(0 to C_OPB_DWIDTH - 1 );
       OPB_select     : in std_logic := '0';
       OPB_RNW        : in std_logic := '0';
       OPB_seqAddr    : in std_logic := '0';
       OPB_BE         : in std_logic_vector(0 to C_OPB_DWIDTH/8 - 1 );
       Sln_xferAck    : out std_logic;
       Sln_errAck     : out std_logic;
       Sln_toutSup    : out std_logic;
       Sln_retry      : out std_logic;

       -- User SystemACE Port

       SysACE_MPA      : out std_logic_vector(6 downto 0);
       SysACE_CLK      : in  std_logic;
       SysACE_MPIRQ    : in  std_logic;
       SysACE_MPD_I    : in  std_logic_vector( C_MEM_WIDTH-1 downto 0);
       SysACE_MPD_O    : out std_logic_vector( C_MEM_WIDTH-1 downto 0);
       SysACE_MPD_T    : out std_logic_vector( C_MEM_WIDTH-1 downto 0);
       SysACE_CEN      : out std_logic;
       SysACE_OEN      : out std_logic;
       SysACE_WEN      : out std_logic;
       SysACE_IRQ      : out std_logic

      );

    --fan-out attributes for XST
    attribute MAX_FANOUT                  : string;
    attribute MAX_FANOUT   of OPB_Clk     : signal is "10000";
    attribute MAX_FANOUT   of OPB_Rst     : signal is "10000";

    -- PSFUtil MPD attributes
    attribute IP_GROUP                    : string;
    attribute IP_GROUP of opb_sysace         : entity is "LOGICORE";
    
    attribute MIN_SIZE                    : string;
    attribute MIN_SIZE of C_BASEADDR      : constant is "0x80";

    attribute SIGIS                       : string;
    attribute SIGIS of OPB_Clk            : signal is "Clk";
    attribute SIGIS of OPB_Rst            : signal is "Rst";
    attribute SIGIS of SysACE_IRQ         : signal is "INTR_LEVEL_HIGH";
    
    attribute ASSIGNMENT                  : string;
    attribute ASSIGNMENT of C_BASEADDR    : constant is "REQUIRE";
    attribute ASSIGNMENT of C_HIGHADDR    : constant is "REQUIRE";
    attribute ASSIGNMENT of C_OPB_DWIDTH  : constant is "CONSTANT";
    attribute ASSIGNMENT of C_OPB_AWIDTH  : constant is "CONSTANT";
    
    attribute XRANGE                      : string;
    attribute XRANGE of C_MEM_WIDTH       : constant is "(8,16)";

      
end entity opb_sysace;


-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of opb_sysace is

-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant MEM_AWIDTH          : integer := 7;        -- change this if SysAce changes

constant OPB_DWIDTH          : integer := C_OPB_DWIDTH;
constant OPB_AWIDTH          : integer := C_OPB_AWIDTH;
constant IPIF_AWIDTH         : integer := C_OPB_AWIDTH;
constant IPIF_DWIDTH         : integer := C_OPB_DWIDTH;
constant ZEROES              : std_logic_vector := X"00000000";
constant SYSACE_ID           : integer := 120;

-------------------- Pipeline Model -------------------------------------------
-- Note: the OPBOUT pipeline registers are always required as the reset to
-- these registers is what guarantees that the Sln_DBus is zero'd at the end
-- of the read transaction

-- for smaller latency and perhaps potentially slower Fmax,
-- include only OPBOUT pipeline registers
-- set the PIPELINE_MODEL constant to 4
--constant PIPELINE_MODEL         : integer := 4; 

-- for 1 clock more latency and perhaps potentially faster Fmax,
-- include OPBIN and OPBOUT pipeline registers
-- set the PIPELINE_MODEL constant to 5
constant PIPELINE_MODEL         : integer := 5; 

constant ARD_ID_ARRAY : INTEGER_ARRAY_TYPE :=
        (
         0 => SYSACE_ID   -- System Ace Base Address  
         );

constant ARD_ADDR_RANGE_ARRAY  : SLV64_ARRAY_TYPE :=
       (
        ZEROES & C_BASEADDR, -- SYSACE Base Address := X"2000_0000"
        ZEROES & C_HIGHADDR  -- SYSACE High Address := X"2FFF_FFFF"
       );

constant ARD_DWIDTH_ARRAY     : INTEGER_ARRAY_TYPE :=
              (
              0 => C_MEM_WIDTH   --  System Ace data width
              );

constant ARD_NUM_CE_ARRAY   : INTEGER_ARRAY_TYPE :=
              (
               0 => 1    -- SYSACE CE number
              );

constant IP_INTR_MODE_ARRAY     : integer_array_type := (1,1);

constant INCLUDE_DEV_ISC : INTEGER := 0;
         -- 'true' specifies that the full device interrupt
         -- source controller structure will be included;
         -- 'false' specifies that only the global interrupt
         -- enable is present in the device interrupt source
         -- controller and that the only source of interrupts
         -- in the device is the IP interrupt source controller

constant INCLUDE_DEV_PENCODER : integer := 0;
         -- 'true' will include the Device IID in the IPIF Interrupt
         -- function

constant IP_MASTER_PRESENT : integer := 0;
         -- 'true' specifies that the IP has Bus Master capability

constant FAMILY : STRING := "virtexe";
          -- Select the target architecture type
                 -- true = Virtex II, false = Virtex E

constant CS_BUS_WIDTH        :  INTEGER := ARD_ADDR_RANGE_ARRAY'LENGTH/2;
constant CE_BUS_WIDTH        :  INTEGER := calc_num_ce(ARD_NUM_CE_ARRAY);
constant IP_NUM_INTR         :  INTEGER := IP_INTR_MODE_ARRAY'length;

-- Zero Constants because (others => '0' does not work in component instantiations)
constant ZERO_AWIDTH         : std_logic_vector(0 to IPIF_AWIDTH - 1) := (others => '0');
constant ZERO_DWIDTH         : std_logic_vector(0 to IPIF_DWIDTH - 1) := (others => '0');
constant ZERO_BE             : std_logic_vector(0 to IPIF_DWIDTH/8 - 1) := (others => '0');
constant ZERO_INTR           : std_logic_vector(0 to IP_NUM_INTR-1) := (others => '0');
constant ONE_POSTED_WRINH    : std_logic_vector(0 to ARD_ID_ARRAY'length-1) 
                                                := (others => '1');
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
-- IPIC Used Signals
signal ip2bus_rdack             : std_logic;
signal ip2bus_wrack             : std_logic;
signal ip2bus_ack               : std_logic_vector(0 to ARD_ID_ARRAY'length-1);
signal ip2bus_toutsup           : std_logic_vector(0 to ARD_ID_ARRAY'length-1);
signal ip2bus_retry             : std_logic_vector(0 to ARD_ID_ARRAY'length-1);
signal ip2bus_errack            : std_logic_vector(0 to ARD_ID_ARRAY'length-1);
signal IP2Bus_Data              : std_logic_vector(0 to IPIF_DWIDTH - 1);
signal Bus2IP_Addr              : std_logic_vector(0 to IPIF_AWIDTH - 1);
signal Bus2IP_Data              : std_logic_vector(0 to IPIF_DWIDTH - 1);
signal Bus2IP_RNW               : std_logic;
signal Bus2IP_CS                : std_logic_vector(0 to ((ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal Bus2IP_RdCE              : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal Bus2IP_WrCE              : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal Bus2IP_BE                : std_logic_vector(0 to (IPIF_DWIDTH / 8) - 1);
signal Bus2IP_Clk               : std_logic;
signal Bus2IP_Reset             : std_logic;
                                
signal  Sln_DBus_i              : std_logic_vector(0 to C_OPB_DWIDTH -1);
signal  Sln_xferAck_i           : std_logic;
signal  Sln_errAck_i            : std_logic;
signal  Sln_toutSup_i           : std_logic;

signal  SYSACE_CEN_i            : std_logic;
signal  SYSACE_OEN_i            : std_logic;
signal  SYSACE_WEN_i            : std_logic;
signal  SYSACE_MPA_i            : std_logic_vector(6 downto 0);
signal  MPA                     : std_logic_vector(0 to 6);
signal  MPD_I                   : std_logic_vector(0 to C_MEM_WIDTH -1);
signal  SYSACE_MPD_O_i          : std_logic_vector(C_MEM_WIDTH-1 downto 0);
signal  MPD_O                   : std_logic_vector(0 to C_MEM_WIDTH -1);
signal  SYSACE_MPD_T_i          : std_logic_vector(C_MEM_WIDTH-1 downto 0);
signal  MPD_T                   : std_logic_vector(0 to C_MEM_WIDTH -1);

-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component opb_ipif 
  generic
  (
    C_ARD_ID_ARRAY              : INTEGER_ARRAY_TYPE         := ( 0 => IPIF_INTR, 1 => IPIF_RST, 2 => USER_00 );
    C_ARD_ADDR_RANGE_ARRAY      : SLV64_ARRAY_TYPE           := ( x"0000_0000_6000_0000", x"0000_0000_6000_003F", x"0000_0000_6000_0040", x"0000_0000_6000_0043", x"0000_0000_6000_0100", x"0000_0000_6000_01FF" );
    C_ARD_DWIDTH_ARRAY          : INTEGER_ARRAY_TYPE         := ( 32, 32, 32 );
    C_ARD_NUM_CE_ARRAY          : INTEGER_ARRAY_TYPE         := ( 16, 1, 8 );
    C_ARD_DEPENDENT_PROPS_ARRAY : DEPENDENT_PROPS_ARRAY_TYPE := ( 0 => (others => 0) ,1 => (others => 0) ,2 => (others => 0) );
    C_PIPELINE_MODEL            : integer                    := 7;
    C_DEV_BLK_ID                : integer                    := 1;
    C_DEV_MIR_ENABLE            : integer                    := 0;
    C_AWIDTH                    : integer                    := 32;
    C_DWIDTH                    : integer                    := 32;
    C_FAMILY                    : string                     := "virtexe";
    C_IP_INTR_MODE_ARRAY        : INTEGER_ARRAY_TYPE         := ( 5, 1 );
    C_INCLUDE_DEV_ISC           : integer                    := 1;
    C_INCLUDE_DEV_IID           : integer                    := 0;
    C_DEV_BURST_ENABLE          : integer                    := 0
  );
  port
  (
    OPB_select         : in  std_logic;
    OPB_DBus           : in  std_logic_vector(0 to C_DWIDTH-1);
    OPB_ABus           : in  std_logic_vector(0 to C_AWIDTH-1);
    OPB_BE             : in  std_logic_vector(0 to C_DWIDTH/8-1);
    OPB_RNW            : in  std_logic;
    OPB_seqAddr        : in  std_logic;
    OPB_xferAck        : in  std_logic;
    Sln_DBus           : out std_logic_vector(0 to C_DWIDTH-1);
    Sln_xferAck        : out std_logic;
    Sln_errAck         : out std_logic;
    Sln_retry          : out std_logic;
    Sln_toutSup        : out std_logic;
    Bus2IP_CS          : out std_logic_vector(0 to C_ARD_ID_ARRAY'length-1);
    Bus2IP_CE          : out std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
    Bus2IP_RdCE        : out std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
    Bus2IP_WrCE        : out std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
    Bus2IP_Data        : out std_logic_vector(0 to C_DWIDTH-1);
    Bus2IP_Addr        : out std_logic_vector(0 to C_AWIDTH-1);
    Bus2IP_BE          : out std_logic_vector(0 to C_DWIDTH/8-1);
    Bus2IP_RNW         : out std_logic;
    Bus2IP_Burst       : out std_logic;
    IP2Bus_Data        : in  std_logic_vector(0 to C_DWIDTH*calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
    IP2Bus_Ack         : in  std_logic_vector(0 to C_ARD_ID_ARRAY'length-1);
    IP2Bus_Error       : in  std_logic_vector(0 to C_ARD_ID_ARRAY'length-1);
    IP2Bus_Retry       : in  std_logic_vector(0 to C_ARD_ID_ARRAY'length-1);
    IP2Bus_ToutSup     : in  std_logic_vector(0 to C_ARD_ID_ARRAY'length-1);
    IP2Bus_PostedWrInh : in  std_logic_vector(0 to C_ARD_ID_ARRAY'length-1);
    OPB_Clk            : in  std_logic;
    Bus2IP_Clk         : out std_logic;
    IP2Bus_Clk         : in  std_logic;
    Reset              : in  std_logic;
    Bus2IP_Reset       : out std_logic;
    IP2Bus_Intr        : in  std_logic_vector(0 to C_IP_INTR_MODE_ARRAY'length-1);
    Device_Intr        : out std_logic
  );
end component opb_ipif;

component sysace
  generic (
    C_BASEADDR                      : std_logic_vector := X"2000_0000";
    C_HIGHADDR                      : std_logic_vector := X"2FFF_FFFF";
    C_IPIF_DWIDTH                   : integer := 64;
    C_IPIF_AWIDTH                   : integer := 32;
    C_MEM_DWIDTH                    : integer := 16;
    C_MEM_AWIDTH                    : integer := 7
    );
  port (
    Bus2IP_Clk             : in  std_logic;
    Bus2IP_Reset           : in  std_logic;

    -- Bus and IPIC Interface signals
    Bus2IP_Addr            : in  std_logic_vector(0 to C_IPIF_AWIDTH-1);
    Bus2IP_BE              : in  std_logic_vector(0 to C_IPIF_DWIDTH/8-1);
    Bus2IP_Data            : in  std_logic_vector(0 to C_IPIF_DWIDTH-1);
    Bus2IP_RNW             : in  std_logic;
    Bus2IP_CS              : in  std_logic;
    Bus2IP_RdCE            : in  std_logic;
    Bus2IP_WrCE            : in  std_logic;

    IP2Bus_Data            : out std_logic_vector(0 to C_IPIF_DWIDTH-1);
    IP2Bus_errAck          : out std_logic;
    IP2Bus_retry           : out std_logic;
    IP2Bus_toutSup         : out std_logic;
    IP2Bus_RdAck           : out std_logic;
    IP2Bus_WrAck           : out std_logic;


    -- Memory signals
    SysACE_MPA             : out std_logic_vector(0 to C_MEM_AWIDTH-1);
    SysACE_CLK             : in  std_logic;
    SysACE_MPD_I           : in  std_logic_vector(0 to C_MEM_DWIDTH-1);
    SysACE_MPD_O           : out std_logic_vector(0 to C_MEM_DWIDTH-1);
    SysACE_MPD_T           : out std_logic_vector(0 to C_MEM_DWIDTH-1);
    SysACE_CEN             : out std_logic;
    SysACE_OEN             : out std_logic;
    SysACE_WEN             : out std_logic    
    );
end component sysace;
  
begin -- architecture IMP

Sln_DBus    <= Sln_DBus_i;
Sln_xferAck <= Sln_xferAck_i;
Sln_toutSup <= Sln_toutSup_i;
Sln_errAck  <= Sln_errAck_i;

-------------------------------------------------------------------------------
-- Change the the Bus2IP/IP2Bus_Data little Endian to SysACE_MPD Big Endian
-------------------------------------------------------------------------------
      SYSACE_MPD_O_i(7)  <= MPD_O(0);
      SYSACE_MPD_O_i(6)  <= MPD_O(1);
      SYSACE_MPD_O_i(5)  <= MPD_O(2);
      SYSACE_MPD_O_i(4)  <= MPD_O(3);
      SYSACE_MPD_O_i(3)  <= MPD_O(4);
      SYSACE_MPD_O_i(2)  <= MPD_O(5);
      SYSACE_MPD_O_i(1)  <= MPD_O(6);
      SYSACE_MPD_O_i(0)  <= MPD_O(7);
      
      SYSACE_MPD_T_i(7)  <= MPD_T(0);
      SYSACE_MPD_T_i(6)  <= MPD_T(1);
      SYSACE_MPD_T_i(5)  <= MPD_T(2);
      SYSACE_MPD_T_i(4)  <= MPD_T(3);
      SYSACE_MPD_T_i(3)  <= MPD_T(4);
      SYSACE_MPD_T_i(2)  <= MPD_T(5);
      SYSACE_MPD_T_i(1)  <= MPD_T(6);
      SYSACE_MPD_T_i(0)  <= MPD_T(7);
      
      MPD_I(0)    <= SYSACE_MPD_I(7);
      MPD_I(1)    <= SYSACE_MPD_I(6);
      MPD_I(2)    <= SYSACE_MPD_I(5);
      MPD_I(3)    <= SYSACE_MPD_I(4);
      MPD_I(4)    <= SYSACE_MPD_I(3);
      MPD_I(5)    <= SYSACE_MPD_I(2);
      MPD_I(6)    <= SYSACE_MPD_I(1);
      MPD_I(7)    <= SYSACE_MPD_I(0);
    
    
    MEM_WIDTH_16_GEN: if C_MEM_WIDTH = 16 generate
      SYSACE_MPD_O_i(15)  <= MPD_O(8);
      SYSACE_MPD_O_i(14)  <= MPD_O(9);
      SYSACE_MPD_O_i(13)  <= MPD_O(10);
      SYSACE_MPD_O_i(12)  <= MPD_O(11);
      SYSACE_MPD_O_i(11)  <= MPD_O(12);
      SYSACE_MPD_O_i(10)  <= MPD_O(13);
      SYSACE_MPD_O_i(9)   <= MPD_O(14);
      SYSACE_MPD_O_i(8)   <= MPD_O(15);
    
      SYSACE_MPD_T_i(15)  <= MPD_T(8);
      SYSACE_MPD_T_i(14)  <= MPD_T(9);
      SYSACE_MPD_T_i(13)  <= MPD_T(10);
      SYSACE_MPD_T_i(12)  <= MPD_T(11);
      SYSACE_MPD_T_i(11)  <= MPD_T(12);
      SYSACE_MPD_T_i(10)  <= MPD_T(13);
      SYSACE_MPD_T_i(9)   <= MPD_T(14);
      SYSACE_MPD_T_i(8)   <= MPD_T(15);
    
      MPD_I(8)     <= SYSACE_MPD_I(15);
      MPD_I(9)     <= SYSACE_MPD_I(14);
      MPD_I(10)    <= SYSACE_MPD_I(13);
      MPD_I(11)    <= SYSACE_MPD_I(12);
      MPD_I(12)    <= SYSACE_MPD_I(11);
      MPD_I(13)    <= SYSACE_MPD_I(10);
      MPD_I(14)    <= SYSACE_MPD_I(9) ;
      MPD_I(15)    <= SYSACE_MPD_I(8) ;
      
    end generate MEM_WIDTH_16_GEN;

SYSACE_MPD_O <=  SYSACE_MPD_O_i ;
SYSACE_MPD_T <=  SYSACE_MPD_T_i ;

-------------------------------------------------------------------------------
-- Change the the Bus2IP_Addr little Endian to SysACE_MPA Big Endian
-------------------------------------------------------------------------------
SYSACE_MPA_i(6) <=  MPA(0);
SYSACE_MPA_i(5) <=  MPA(1);
SYSACE_MPA_i(4) <=  MPA(2);
SYSACE_MPA_i(3) <=  MPA(3);
SYSACE_MPA_i(2) <=  MPA(4);
SYSACE_MPA_i(1) <=  MPA(5);
SYSACE_MPA_i(0) <=  MPA(6);
SYSACE_MPA      <=  SYSACE_MPA_i  ;



SYSACE_CEN   <=  SYSACE_CEN_i  ;
SYSACE_OEN   <=  SYSACE_OEN_i  ;
SYSACE_WEN   <=  SYSACE_WEN_i  ;
SYSACE_IRQ   <=  SysACE_MPIRQ  ;

-- generate single IPIC acknowledge
ip2bus_ack(0)   <= ip2bus_rdack or ip2bus_wrack;
-------------------------------------------------------------------------------
-- Component Instantiations
-------------------------------------------------------------------------------
I_OPB_IPIF: opb_ipif
  generic map(
      -- Generics to be set for ipif
      C_ARD_ID_ARRAY                 =>   ARD_ID_ARRAY          ,
      C_ARD_ADDR_RANGE_ARRAY         =>   ARD_ADDR_RANGE_ARRAY  ,
      C_ARD_DWIDTH_ARRAY             =>   ARD_DWIDTH_ARRAY      ,
      C_ARD_NUM_CE_ARRAY             =>   ARD_NUM_CE_ARRAY      ,
      C_PIPELINE_MODEL               =>   PIPELINE_MODEL        ,
      C_DEV_BLK_ID                   =>   1                     ,
      C_DEV_MIR_ENABLE               =>   0                     ,
      C_AWIDTH                       =>   OPB_AWIDTH            ,
      C_DWIDTH                       =>   OPB_DWIDTH            ,
      C_FAMILY                       =>   FAMILY                ,
      C_IP_INTR_MODE_ARRAY           =>   IP_INTR_MODE_ARRAY    ,
      C_INCLUDE_DEV_ISC              =>   0                     ,
      C_INCLUDE_DEV_IID              =>   0                     ,
      C_DEV_BURST_ENABLE             =>   0
      )
    port map (

        OPB_select             => OPB_select,
        OPB_DBus               => OPB_DBus,
        OPB_ABus               => OPB_ABus,
        OPB_BE                 => OPB_BE,
        OPB_RNW                => OPB_RNW,
        OPB_seqAddr            => OPB_seqAddr,
        OPB_xferAck            => '0',
        Sln_DBus               => Sln_DBus_i,
        Sln_xferAck            => Sln_xferAck_i,
        Sln_errAck             => Sln_errAck_i,
        Sln_retry              => Sln_retry,
        Sln_toutSup            => Sln_toutSup_i,
        Bus2IP_CS              => Bus2IP_CS,
        Bus2IP_CE              => open,
        Bus2IP_RdCE            => Bus2IP_RdCE,
        Bus2IP_WrCE            => Bus2IP_WrCE,
        Bus2IP_Data            => Bus2IP_Data,
        Bus2IP_Addr            => Bus2IP_Addr,
        Bus2IP_BE              => Bus2IP_BE,
        Bus2IP_RNW             => Bus2IP_RNW,
        Bus2IP_Burst           => open,
        IP2Bus_Data            => IP2Bus_Data,
        IP2Bus_Ack             => ip2bus_ack,
        IP2Bus_Error           => ip2bus_errack,
        IP2Bus_Retry           => ip2bus_retry,
        IP2Bus_ToutSup         => ip2bus_toutsup,
        IP2Bus_PostedWrInh     => ONE_POSTED_WRINH,
        OPB_Clk                => OPB_Clk,
        Bus2IP_Clk             => Bus2IP_Clk,
        IP2Bus_Clk             => '0',
        Reset                  => OPB_Rst,
        Bus2IP_Reset           => Bus2IP_Reset,
        IP2Bus_Intr            => ZERO_INTR,
        Device_Intr            => open
      );

-------------------------------------------------------------------------------
-- Generate SYSACE controller
-------------------------------------------------------------------------------

I_SYSACE_CONTROLLER: sysace
  generic map(
       C_BASEADDR     =>  C_BASEADDR,
       C_HIGHADDR     =>  C_HIGHADDR,
       C_IPIF_DWIDTH  =>  C_OPB_DWIDTH,
       C_IPIF_AWIDTH  =>  C_OPB_AWIDTH,
       C_MEM_DWIDTH   =>  C_MEM_WIDTH,
       C_MEM_AWIDTH   =>  MEM_AWIDTH
       )
    port map (
       Bus2IP_Reset         =>  Bus2IP_Reset,
       Bus2IP_Clk           =>  Bus2IP_Clk,
       Bus2IP_Addr          =>  Bus2IP_Addr,
       Bus2IP_BE            =>  Bus2IP_BE,
       Bus2IP_Data          =>  Bus2IP_Data,
       Bus2IP_RNW           =>  Bus2IP_RNW,
       Bus2IP_CS            =>  Bus2IP_CS(0),
       Bus2IP_RdCE          =>  Bus2IP_RdCE(0),
       Bus2IP_WrCE          =>  Bus2IP_WrCE(0),

       IP2Bus_Data          => IP2Bus_Data,
       IP2Bus_errAck        => ip2bus_errack(0),
       IP2Bus_retry         => ip2bus_retry(0),
       IP2Bus_toutSup       => ip2bus_toutsup(0),
       IP2Bus_RdAck         => ip2bus_rdack,
       IP2Bus_WrAck         => ip2bus_wrack,
                         
       SysACE_MPA           => MPA,    
       SysACE_CLK           => SysACE_CLK,    
       SysACE_MPD_I         => MPD_I,   
       SysACE_MPD_O         => MPD_O,   
       SysACE_MPD_T         => MPD_T,   
       SysACE_CEN           => SysACE_CEN_i,    
       SysACE_OEN           => SysACE_OEN_i,    
       SysACE_WEN           => SysACE_WEN_i    
       );

-------------------------------------------------------------------

end implementation;
