//-----------------------------------------------------------------------------
// clocks_0_wrapper.v
//-----------------------------------------------------------------------------

module clocks_0_wrapper
  (
    sys_clk,
    sysace_clk,
    tft_clk,
    dcm_rst_n,
    plb_clk,
    plb_clk_n,
    plb_clk90,
    plb_clk270,
    opb_clk,
    dcr_clk,
    ddr_fb_clk,
    ddr_fb_clk90,
    ddr_fb_clk270,
    dcm_locked,
    sram_clk,
    sram_clk_fb
  );
  input sys_clk;
  input sysace_clk;
  output tft_clk;
  input dcm_rst_n;
  output plb_clk;
  output plb_clk_n;
  output plb_clk90;
  output plb_clk270;
  output opb_clk;
  output dcr_clk;
  input ddr_fb_clk;
  output ddr_fb_clk90;
  output ddr_fb_clk270;
  output dcm_locked;
  output sram_clk;
  input sram_clk_fb;

  clocks
    clocks_0 (
      .sys_clk ( sys_clk ),
      .sysace_clk ( sysace_clk ),
      .tft_clk ( tft_clk ),
      .dcm_rst_n ( dcm_rst_n ),
      .plb_clk ( plb_clk ),
      .plb_clk_n ( plb_clk_n ),
      .plb_clk90 ( plb_clk90 ),
      .plb_clk270 ( plb_clk270 ),
      .opb_clk ( opb_clk ),
      .dcr_clk ( dcr_clk ),
      .ddr_fb_clk ( ddr_fb_clk ),
      .ddr_fb_clk90 ( ddr_fb_clk90 ),
      .ddr_fb_clk270 ( ddr_fb_clk270 ),
      .dcm_locked ( dcm_locked ),
      .sram_clk ( sram_clk ),
      .sram_clk_fb ( sram_clk_fb )
    );

endmodule

// synthesis attribute x_core_info of clocks_0_wrapper is clocks_v1_00_c;

