-------------------------------------------------------------------------------
-- mdm.vhd - Entity and architecture
--
--  ***************************************************************************
--  **  Copyright(C) 2003 by Xilinx, Inc. All rights reserved.               **
--  **                                                                       **
--  **  This text contains proprietary, confidential                         **
--  **  information of Xilinx, Inc. , is distributed by                      **
--  **  under license from Xilinx, Inc., and may be used,                    **
--  **  copied and/or disclosed only pursuant to the terms                   **
--  **  of a valid license agreement with Xilinx, Inc.                       **
--  **                                                                       **
--  **  Unmodified source code is guaranteed to place and route,             **
--  **  function and run at speed according to the datasheet                 **
--  **  specification. Source code is provided "as-is", with no              **
--  **  obligation on the part of Xilinx to provide support.                 **
--  **                                                                       **
--  **  Xilinx Hotline support of source code IP shall only include          **
--  **  standard level Xilinx Hotline support, and will only address         **
--  **  issues and questions related to the standard released Netlist        **
--  **  version of the core (and thus indirectly, the original core source). **
--  **                                                                       **
--  **  The Xilinx Support Hotline does not have access to source            **
--  **  code and therefore cannot answer specific questions related          **
--  **  to source HDL. The Xilinx Support Hotline will only be able          **
--  **  to confirm the problem in the Netlist version of the core.           **
--  **                                                                       **
--  **  This copyright and support notice must be retained as part           **
--  **  of this text at all times.                                           **
--  ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename:        mdm.vhd
--
-- Description:     
--                  
-- VHDL-Standard:   VHDL'93
-------------------------------------------------------------------------------
-- Structure:   
--              mdm.vhd
--
-------------------------------------------------------------------------------
-- Author:          goran
-- Revision:        $Revision: 1.2 $
-- Date:            $Date: 2004/11/19 21:28:09 $
--
-- History:
--   goran  2003-02-13    First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "clk_div#", "clk_#x" 
--      reset signals:                          "rst", "rst_n" 
--      generics:                               "C_*" 
--      user defined types:                     "*_TYPE" 
--      state machine next state:               "*_ns" 
--      state machine current state:            "*_cs" 
--      combinatorial signals:                  "*_com" 
--      pipelined or register delay signals:    "*_d#" 
--      counter signals:                        "*cnt*"
--      clock enable signals:                   "*_ce" 
--      internal version of output port         "*_i"
--      device pins:                            "*_pin" 
--      ports:                                  - Names begin with Uppercase 
--      processes:                              "*_PROCESS" 
--      component instantiations:               "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

entity OPB_MDM is
  generic (
    C_OPB_AWIDTH      : integer                   := 32;
    C_OPB_DWIDTH      : integer                   := 32;
    C_BASEADDR        : std_logic_vector(0 to 31) := X"FFFF_8000";
    C_HIGHADDR        : std_logic_vector(0 to 31) := X"FFFF_80FF";
    C_FAMILY          : string                    := "virtex2";
    C_MB_DBG_PORTS    : integer                   := 1;
    C_USE_UART        : integer                   := 1;
    C_UART_WIDTH      : integer                   := 32;
    C_WRITE_FSL_PORTS : integer                   := 0
    );
  port (
    -- Global signals
    OPB_Clk           : in std_logic;
    OPB_Rst           : in std_logic;

    Interrupt     : out std_logic;
    Ext_BRK       : out std_logic;
    Ext_NM_BRK    : out std_logic;
    Debug_SYS_Rst : out std_logic;
    Debug_Rst     : out std_logic;

    -- OPB signals
    OPB_ABus    : in std_logic_vector(0 to 31);
    OPB_BE      : in std_logic_vector(0 to 3);
    OPB_RNW     : in std_logic;
    OPB_select  : in std_logic;
    OPB_seqAddr : in std_logic;
    OPB_DBus    : in std_logic_vector(0 to 31);

    MDM_DBus    : out std_logic_vector(0 to 31);
    MDM_errAck  : out std_logic;
    MDM_retry   : out std_logic;
    MDM_toutSup : out std_logic;
    MDM_xferAck : out std_logic;

    -- MicroBlaze Debug Signals
    Dbg_Clk_0     : out std_logic;
    Dbg_TDI_0     : out std_logic;
    Dbg_TDO_0     : in  std_logic;
    Dbg_Reg_En_0  : out std_logic_vector(0 to 4);
    Dbg_Capture_0 : out std_logic;
    Dbg_Update_0  : out std_logic;

    Dbg_Clk_1     : out std_logic;
    Dbg_TDI_1     : out std_logic;
    Dbg_TDO_1     : in  std_logic;
    Dbg_Reg_En_1  : out std_logic_vector(0 to 4);
    Dbg_Capture_1 : out std_logic;
    Dbg_Update_1  : out std_logic;

    Dbg_Clk_2     : out std_logic;
    Dbg_TDI_2     : out std_logic;
    Dbg_TDO_2     : in  std_logic;
    Dbg_Reg_En_2  : out std_logic_vector(0 to 4);
    Dbg_Capture_2 : out std_logic;
    Dbg_Update_2  : out std_logic;

    Dbg_Clk_3     : out std_logic;
    Dbg_TDI_3     : out std_logic;
    Dbg_TDO_3     : in  std_logic;
    Dbg_Reg_En_3  : out std_logic_vector(0 to 4);
    Dbg_Capture_3 : out std_logic;
    Dbg_Update_3  : out std_logic;

    Dbg_Clk_4     : out std_logic;
    Dbg_TDI_4     : out std_logic;
    Dbg_TDO_4     : in  std_logic;
    Dbg_Reg_En_4  : out std_logic_vector(0 to 4);
    Dbg_Capture_4 : out std_logic;
    Dbg_Update_4  : out std_logic;

    Dbg_Clk_5     : out std_logic;
    Dbg_TDI_5     : out std_logic;
    Dbg_TDO_5     : in  std_logic;
    Dbg_Reg_En_5  : out std_logic_vector(0 to 4);
    Dbg_Capture_5 : out std_logic;
    Dbg_Update_5  : out std_logic;

    Dbg_Clk_6     : out std_logic;
    Dbg_TDI_6     : out std_logic;
    Dbg_TDO_6     : in  std_logic;
    Dbg_Reg_En_6  : out std_logic_vector(0 to 4);
    Dbg_Capture_6 : out std_logic;
    Dbg_Update_6  : out std_logic;

    Dbg_Clk_7     : out std_logic;
    Dbg_TDI_7     : out std_logic;
    Dbg_TDO_7     : in  std_logic;
    Dbg_Reg_En_7  : out std_logic_vector(0 to 4);
    Dbg_Capture_7 : out std_logic;
    Dbg_Update_7  : out std_logic;

-- Connect the BSCAN's USER1 + common signals to the external pins
-- These signals can be connected to an ICON core instantiated by the user
-- Will not be used if the ICON is inserted within the mdm

    bscan_tdi     : out std_logic;
    bscan_reset   : out std_logic;
    bscan_shift   : out std_logic;
    bscan_update  : out std_logic;
    bscan_capture : out std_logic;
    bscan_sel1    : out std_logic;
    bscan_drck1   : out std_logic;
    bscan_tdo1    : in  std_logic;

    ---------------------------------------------------------------------------
    -- FSL ports
    ---------------------------------------------------------------------------

    FSL0_S_Clk     : out std_logic;
    FSL0_S_Read    : out std_logic;
    FSL0_S_Data    : in  std_logic_vector(0 to 31);
    FSL0_S_Control : in  std_logic;
    FSL0_S_Exists  : in  std_logic;

    FSL0_M_Clk     : out std_logic;
    FSL0_M_Write   : out std_logic;
    FSL0_M_Data    : out std_logic_vector(0 to 31);
    FSL0_M_Control : out std_logic;
    FSL0_M_Full    : in  std_logic

    );

end entity OPB_MDM;

library unisim;
use unisim.vcomponents.all;

library opb_mdm_v2_01_a;
use opb_mdm_v2_01_a.all;

library proc_common_v1_00_c;
use proc_common_v1_00_c.family.all;

architecture IMP of OPB_MDM is

  constant C_FSL_DATA_SIZE : integer := 32;

  attribute BOX_TYPE : string;

  -- component BUFG is
  --   port (
  --     O : out std_logic;
  --     I : in  std_logic);
  -- end component;

  component BSCAN_VIRTEX
    port
      (
        TDO1   : in  std_logic;
        TDO2   : in  std_logic;
        UPDATE : out std_logic;
        SHIFT  : out std_logic;
        RESET  : out std_logic;
        TDI    : out std_logic;
        SEL1   : out std_logic;
        DRCK1  : out std_logic;
        SEL2   : out std_logic;
        DRCK2  : out std_logic
        );
  end component;
  attribute BOX_TYPE of BSCAN_VIRTEX : component is "black_box";

  -- component BSCAN_VIRTEX2
  --   port
  --     (
  --       TDO1    : in  std_logic;
  --       TDO2    : in  std_logic;
  --       UPDATE  : out std_logic;
  --       SHIFT   : out std_logic;
  --       RESET   : out std_logic;
  --       TDI     : out std_logic;
  --       SEL1    : out std_logic;
  --       DRCK1   : out std_logic;
  --       SEL2    : out std_logic;
  --       DRCK2   : out std_logic;
  --       CAPTURE : out std_logic
  --       );
  -- end component;
  -- attribute BOX_TYPE of BSCAN_VIRTEX2 : component is "black_box";

  component BSCAN_VIRTEX4
    generic (
      JTAG_CHAIN : integer := 1
      );
    port
      (
        TDO     : in  std_logic;
        CAPTURE : out std_logic;
        DRCK    : out std_logic;
        RESET   : out std_logic;
        SEL     : out std_logic;
        SHIFT   : out std_logic;
        TDI     : out std_logic;
        UPDATE  : out std_logic
        );
  end component;
  attribute box_type of BSCAN_VIRTEX4: component is "black_box";

  component MDM_Core is
    generic (
      C_BASEADDR      : std_logic_vector(0 to 31);
      C_HIGHADDR      : std_logic_vector(0 to 31);
      C_MB_DBG_PORTS  : integer;
      C_USE_UART      : integer;
      C_UART_WIDTH    : integer;
      C_USE_FSL       : integer := 0;
      C_FSL_DATA_SIZE : integer := 32
      );
    port (
      -- Global signals
      OPB_Clk : in std_logic;
      OPB_Rst : in std_logic;

      Interrupt     : out std_logic;
      Ext_BRK       : out std_logic;
      Ext_NM_BRK    : out std_logic;
      Debug_SYS_Rst : out std_logic;
      Debug_Rst     : out std_logic;

      -- OPB signals
      OPB_ABus    : in std_logic_vector(0 to 31);
      OPB_BE      : in std_logic_vector(0 to 3);
      OPB_RNW     : in std_logic;
      OPB_select  : in std_logic;
      OPB_seqAddr : in std_logic;
      OPB_DBus    : in std_logic_vector(0 to 31);

      MDM_DBus    : out std_logic_vector(0 to 31);
      MDM_errAck  : out std_logic;
      MDM_retry   : out std_logic;
      MDM_toutSup : out std_logic;
      MDM_xferAck : out std_logic;

      -- JTAG signals
      TDI    : in  std_logic;
      RESET  : in  std_logic;
      UPDATE : in  std_logic;
      SHIFT  : in  std_logic;
      SEL    : in  std_logic;
      DRCK   : in  std_logic;
      TDO    : out std_logic;

      -- MicroBlaze Debug Signals
      Dbg_Clk_0     : out std_logic;
      Dbg_TDI_0     : out std_logic;
      Dbg_TDO_0     : in  std_logic;
      Dbg_Reg_En_0  : out std_logic_vector(0 to 4);
      Dbg_Capture_0 : out std_logic;
      Dbg_Update_0  : out std_logic;

      Dbg_Clk_1     : out std_logic;
      Dbg_TDI_1     : out std_logic;
      Dbg_TDO_1     : in  std_logic;
      Dbg_Reg_En_1  : out std_logic_vector(0 to 4);
      Dbg_Capture_1 : out std_logic;
      Dbg_Update_1  : out std_logic;

      Dbg_Clk_2     : out std_logic;
      Dbg_TDI_2     : out std_logic;
      Dbg_TDO_2     : in  std_logic;
      Dbg_Reg_En_2  : out std_logic_vector(0 to 4);
      Dbg_Capture_2 : out std_logic;
      Dbg_Update_2  : out std_logic;

      Dbg_Clk_3     : out std_logic;
      Dbg_TDI_3     : out std_logic;
      Dbg_TDO_3     : in  std_logic;
      Dbg_Reg_En_3  : out std_logic_vector(0 to 4);
      Dbg_Capture_3 : out std_logic;
      Dbg_Update_3  : out std_logic;

      Dbg_Clk_4     : out std_logic;
      Dbg_TDI_4     : out std_logic;
      Dbg_TDO_4     : in  std_logic;
      Dbg_Reg_En_4  : out std_logic_vector(0 to 4);
      Dbg_Capture_4 : out std_logic;
      Dbg_Update_4  : out std_logic;

      Dbg_Clk_5     : out std_logic;
      Dbg_TDI_5     : out std_logic;
      Dbg_TDO_5     : in  std_logic;
      Dbg_Reg_En_5  : out std_logic_vector(0 to 4);
      Dbg_Capture_5 : out std_logic;
      Dbg_Update_5  : out std_logic;

      Dbg_Clk_6     : out std_logic;
      Dbg_TDI_6     : out std_logic;
      Dbg_TDO_6     : in  std_logic;
      Dbg_Reg_En_6  : out std_logic_vector(0 to 4);
      Dbg_Capture_6 : out std_logic;
      Dbg_Update_6  : out std_logic;

      Dbg_Clk_7     : out std_logic;
      Dbg_TDI_7     : out std_logic;
      Dbg_TDO_7     : in  std_logic;
      Dbg_Reg_En_7  : out std_logic_vector(0 to 4);
      Dbg_Capture_7 : out std_logic;
      Dbg_Update_7  : out std_logic;

      FSL0_S_Clk     : out std_logic;
      FSL0_S_Read    : out std_logic;
      FSL0_S_Data    : in  std_logic_vector(0 to C_FSL_DATA_SIZE-1);
      FSL0_S_Control : in  std_logic;
      FSL0_S_Exists  : in  std_logic;
      FSL0_M_Clk     : out std_logic;
      FSL0_M_Write   : out std_logic;
      FSL0_M_Data    : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
      FSL0_M_Control : out std_logic;
      FSL0_M_Full    : in  std_logic;

      jtag_clk : out std_logic;
      trig     : out std_logic_vector(7 downto 0);
      data     : out std_logic_vector(31 downto 0)
      );
  end component MDM_Core;

  -- The only difference between BSCAN_VIRTEX and BSCAN_VIRTEX2 is the
  -- addition of the CAPTURE output which is not being used.
  --
  -- constant Virtex2_Based : boolean := (derived(C_FAMILY,virtex2p) and
  --                                      not derived(C_FAMILY,virtex));
  -- This was always false:
  -- constant Virtex2_Based : boolean := false;
  --
  -- Virtex2 works fine with the Virtex version
  -- constant Virtex_Based : boolean := not Virtex4_Based and not Virtex2_Based;

  constant Virtex4_Based : boolean := equalIgnoreCase(C_FAMILY, "virtex4");

  constant Virtex_Based : boolean := not Virtex4_Based;

  -- MDM signals
  signal tdi     : std_logic;
  signal reset   : std_logic;
  signal update  : std_logic;
  signal capture : std_logic;
  signal shift   : std_logic;
  signal sel     : std_logic;
  signal drck    : std_logic;
  signal drck_i  : std_logic;
  signal tdo     : std_logic;

  signal tdo1    : std_logic;
  signal sel1    : std_logic;
  signal drck1_i : std_logic;
  signal drck1   : std_logic;

  attribute period           : string;
  attribute period of drck_i : signal is "80";
  
begin  -- architecture IMP

  -- Connect USER1 signal to external ports
  tdo1 <= bscan_tdo1;

  bscan_drck1  <= drck1;
  bscan_sel1   <= sel1;
  bscan_tdi    <= tdi;
  bscan_reset  <= reset;
  bscan_shift  <= shift;
  bscan_update <= update;
  bscan_capture <= capture;
  
  Using_Virtex : if (Virtex_Based) generate
    BSCAN_VIRTEX_I : BSCAN_VIRTEX
      port map (
        TDO1   => tdo1,                 -- [in  std_logic]
        TDO2   => tdo,                  -- [in  std_logic]
        UPDATE => update,               -- [out std_logic]
        SHIFT  => shift,                -- [out std_logic]
        RESET  => reset,                -- [out std_logic]
        TDI    => tdi,                  -- [out std_logic]
        SEL1   => sel1,                 -- [out std_logic]
        DRCK1  => drck1_i,              -- [out std_logic]
        SEL2   => sel,                  -- [out std_logic]
        DRCK2  => drck_i);              -- [out std_logic]

    capture <= '0';               -- Ground unconnected pin
    
  end generate Using_Virtex;

  -- The only difference between BSCAN_VIRTEX and BSCAN_VIRTEX2
  -- is the addition of the CAPTURE output which is being left open
  --
  -- Using_Virtex2 : if (Virtex2_Based) generate
  --   BSCAN_VIRTEX2_I : BSCAN_VIRTEX2
  --     port map (
  --       TDO1    => bscan_tdo1,          -- [in  std_logic]
  --       TDO2    => tdo,                 -- [in  std_logic]
  --       UPDATE  => update,              -- [out std_logic]
  --       SHIFT   => shift,               -- [out std_logic]
  --       RESET   => reset,               -- [out std_logic]
  --       TDI     => tdi,                 -- [out std_logic]
  --       SEL1    => bscan_sel1,          -- [out std_logic]
  --       DRCK1   => bscan_drck1,         -- [out std_logic]
  --       SEL2    => sel,                 -- [out std_logic]
  --       DRCK2   => drck_i,              -- [out std_logic]
  --       CAPTURE => capture);            -- [out std_logic]
  -- 
  -- end generate Using_Virtex2;

  Using_Virtex4 : if (Virtex4_Based) generate
    BSCAN_VIRTEX4_I : BSCAN_VIRTEX4
      generic map (
        JTAG_CHAIN => 1)
      port map (
        TDO    => tdo,                  -- [in  std_logic]
        UPDATE => update,               -- [out std_logic]
        SHIFT  => shift,                -- [out std_logic]
        RESET  => reset,                -- [out std_logic]
        TDI    => tdi,                  -- [out std_logic]
        SEL    => sel,                  -- [out std_logic]
        DRCK   => drck_i,               -- [out std_logic]
        CAPTURE => capture);            -- [out std_logic]

    -- Ground signals pretending to be CHAIN 1
    -- This does not actually use CHAIN 1
    sel1 <= '0';
    drck1_i <= '0';

    -- tdo1 is unused

  end generate Using_Virtex4;

  BUFG_DRCK1 : BUFG
    port map (
      O => drck1,                       -- [out std_logic]
      I => drck1_i);                    -- [in std_logic]
  
  BUFG_DRCK2 : BUFG
    port map (
      O => drck,
      I => drck_i);

  MDM_Core_I1 : MDM_Core
    generic map (
      C_BASEADDR      => C_BASEADDR,         -- [std_logic_vector(0 to 31)]
      C_HIGHADDR      => C_HIGHADDR,         -- [std_logic_vector(0 to 31)]
      C_MB_DBG_PORTS  => C_MB_DBG_PORTS,     -- [integer]
      C_USE_UART      => C_USE_UART,         -- [integer]
      C_UART_WIDTH    => C_UART_WIDTH,       -- [integer]
      C_USE_FSL       => C_WRITE_FSL_PORTS,  -- [integer]
      C_FSL_DATA_SIZE => C_FSL_DATA_SIZE)    -- [integer]
    port map (
      -- Global signals
      OPB_Clk         => OPB_Clk,            -- [in  std_logic]
      OPB_Rst         => OPB_Rst,            -- [in  std_logic]

      Interrupt     => Interrupt,  -- [out std_logic]
      Ext_BRK       => Ext_BRK,  -- [out std_logic]
      Ext_NM_BRK    => Ext_NM_BRK,  -- [out std_logic]
      Debug_SYS_Rst => Debug_SYS_Rst,  -- [out std_logic]
      Debug_Rst     => Debug_Rst,  -- [out std_logic]

      -- OPB signals
      OPB_ABus    => OPB_ABus,  -- [in  std_logic_vector(0 to 31)]
      OPB_BE      => OPB_BE,  -- [in  std_logic_vector(0 to 3)]
      OPB_RNW     => OPB_RNW,  -- [in  std_logic]
      OPB_select  => OPB_select,  -- [in  std_logic]
      OPB_seqAddr => OPB_seqAddr,  -- [in  std_logic]
      OPB_DBus    => OPB_DBus,  -- [in  std_logic_vector(0 to 31)]

      MDM_DBus    => MDM_DBus,  -- [out std_logic_vector(0 to 31)]
      MDM_errAck  => MDM_errAck,  -- [out std_logic]
      MDM_retry   => MDM_retry,  -- [out std_logic]
      MDM_toutSup => MDM_toutSup,  -- [out std_logic]
      MDM_xferAck => MDM_xferAck,  -- [out std_logic]

      -- JTAG signals
      TDI    => tdi,  -- [in  std_logic]
      RESET  => reset,  -- [in  std_logic]
      UPDATE => update,  -- [in  std_logic]
      SHIFT  => shift,  -- [in  std_logic]
      SEL    => sel,  -- [in  std_logic]
      DRCK   => drck,  -- [in  std_logic]
      TDO    => tdo,  -- [out std_logic]

      -- MicroBlaze Debug Signals
      Dbg_Clk_0     => Dbg_Clk_0,  -- [out std_logic]
      Dbg_TDI_0     => Dbg_TDI_0,  -- [out std_logic]
      Dbg_TDO_0     => Dbg_TDO_0,  -- [in  std_logic]
      Dbg_Reg_En_0  => Dbg_Reg_En_0,  -- [out std_logic_vector(0 to 3)]
      Dbg_Capture_0 => Dbg_Capture_0,  -- [out std_logic]
      Dbg_Update_0  => Dbg_Update_0,  -- [out std_logic]

      Dbg_Clk_1     => Dbg_Clk_1,  -- [out std_logic]
      Dbg_TDI_1     => Dbg_TDI_1,  -- [out std_logic]
      Dbg_TDO_1     => Dbg_TDO_1,  -- [in  std_logic]
      Dbg_Reg_En_1  => Dbg_Reg_En_1,  -- [out std_logic_vector(0 to 3)]
      Dbg_Capture_1 => Dbg_Capture_1,  -- [out std_logic]
      Dbg_Update_1  => Dbg_Update_1,  -- [out std_logic]

      Dbg_Clk_2     => Dbg_Clk_2,  -- [out std_logic]
      Dbg_TDI_2     => Dbg_TDI_2,  -- [out std_logic]
      Dbg_TDO_2     => Dbg_TDO_2,  -- [in  std_logic]
      Dbg_Reg_En_2  => Dbg_Reg_En_2,  -- [out std_logic_vector(0 to 3)]
      Dbg_Capture_2 => Dbg_Capture_2,  -- [out std_logic]
      Dbg_Update_2  => Dbg_Update_2,  -- [out std_logic]

      Dbg_Clk_3     => Dbg_Clk_3,  -- [out std_logic]
      Dbg_TDI_3     => Dbg_TDI_3,  -- [out std_logic]
      Dbg_TDO_3     => Dbg_TDO_3,  -- [in  std_logic]
      Dbg_Reg_En_3  => Dbg_Reg_En_3,  -- [out std_logic_vector(0 to 3)]
      Dbg_Capture_3 => Dbg_Capture_3,  -- [out std_logic]
      Dbg_Update_3  => Dbg_Update_3,  -- [out std_logic]

      Dbg_Clk_4     => Dbg_Clk_4,  -- [out std_logic]
      Dbg_TDI_4     => Dbg_TDI_4,  -- [out std_logic]
      Dbg_TDO_4     => Dbg_TDO_4,  -- [in  std_logic]
      Dbg_Reg_En_4  => Dbg_Reg_En_4,  -- [out std_logic_vector(0 to 3)]
      Dbg_Capture_4 => Dbg_Capture_4,  -- [out std_logic]
      Dbg_Update_4  => Dbg_Update_4,  -- [out std_logic]

      Dbg_Clk_5     => Dbg_Clk_5,  -- [out std_logic]
      Dbg_TDI_5     => Dbg_TDI_5,  -- [out std_logic]
      Dbg_TDO_5     => Dbg_TDO_5,  -- [in  std_logic]
      Dbg_Reg_En_5  => Dbg_Reg_En_5,  -- [out std_logic_vector(0 to 3)]
      Dbg_Capture_5 => Dbg_Capture_5,  -- [out std_logic]
      Dbg_Update_5  => Dbg_Update_5,  -- [out std_logic]

      Dbg_Clk_6     => Dbg_Clk_6,  -- [out std_logic]
      Dbg_TDI_6     => Dbg_TDI_6,  -- [out std_logic]
      Dbg_TDO_6     => Dbg_TDO_6,  -- [in  std_logic]
      Dbg_Reg_En_6  => Dbg_Reg_En_6,  -- [out std_logic_vector(0 to 3)]
      Dbg_Capture_6 => Dbg_Capture_6,  -- [out std_logic]
      Dbg_Update_6  => Dbg_Update_6,  -- [out std_logic]

      Dbg_Clk_7     => Dbg_Clk_7,  -- [out std_logic]
      Dbg_TDI_7     => Dbg_TDI_7,  -- [out std_logic]
      Dbg_TDO_7     => Dbg_TDO_7,  -- [in  std_logic]
      Dbg_Reg_En_7  => Dbg_Reg_En_7,  -- [out std_logic_vector(0 to 3)]
      Dbg_Capture_7 => Dbg_Capture_7,  -- [out std_logic]
      Dbg_Update_7  => Dbg_Update_7,  -- [out std_logic]

      FSL0_S_Clk     => FSL0_S_Clk,
      FSL0_S_Read    => FSL0_S_Read,
      FSL0_S_Data    => FSL0_S_Data,
      FSL0_S_Control => FSL0_S_Control,
      FSL0_S_Exists  => FSL0_S_Exists,
      FSL0_M_Clk     => FSL0_M_Clk,
      FSL0_M_Write   => FSL0_M_Write,
      FSL0_M_Data    => FSL0_M_Data,
      FSL0_M_Control => FSL0_M_Control,
      FSL0_M_Full    => FSL0_M_Full,

      jtag_clk => open,
      trig     => open,
      data     => open
      );

end architecture IMP;

