//-----------------------------------------------------------------------------
// system.v
//-----------------------------------------------------------------------------

module system
  (
    sys_clk_in,
    sys_rst_in,
    uart_RX,
    uart_TX,
    gpio,
    gpio_exp_hdr1,
    gpio_exp_hdr2,
    gpio_char_lcd,
    ps2_mouse_clk,
    ps2_mouse_data,
    ps2_keyb_clk,
    ps2_keyb_data,
    iic_scl,
    iic_sda,
    ac97_reset_n,
    ac97_sdata_In,
    ac97_sdata_Out,
    ac97_sync,
    ac97_bit_clk,
    phy_rst_n,
    phy_mii_int_n,
    phy_col,
    phy_crs,
    phy_dv,
    phy_mii_clk,
    phy_mii_data,
    phy_rx_clk,
    phy_rx_data,
    phy_rx_er,
    phy_tx_clk,
    phy_tx_data,
    phy_tx_en,
    phy_tx_er,
    ddr_clk_fb,
    ddr_ad,
    ddr_ba,
    ddr_casb,
    ddr_cke,
    ddr_clk,
    ddr_clkb,
    ddr_csb,
    ddr_dm,
    ddr_dq,
    ddr_dqs,
    ddr_rasb,
    ddr_web,
    tft_lcd_b,
    tft_lcd_clk,
    tft_lcd_g,
    tft_lcd_hsync,
    tft_lcd_r,
    tft_lcd_vsync,
    opb_error,
    plb_error,
    sram_clk,
    sram_clk_fb,
    flash_a23,
    sram_flash_addr,
    sram_flash_data,
    sram_cen,
    sram_flash_oe_n,
    sram_flash_we_n,
    sram_bw,
    flash_ce,
    sram_adv_ld_n,
    sram_mode,
    sysace_clk_in,
    sysace_mpirq,
    sace_mpce,
    usb_hpi_reset_n,
    usb_hpi_int,
    usb_csn,
    sace_usb_a,
    sace_usb_d,
    sace_usb_oen,
    sace_usb_wen
  );
  input sys_clk_in;
  input sys_rst_in;
  input uart_RX;
  output uart_TX;
  inout [26:0] gpio;
  inout [31:0] gpio_exp_hdr1;
  inout [31:0] gpio_exp_hdr2;
  inout [6:0] gpio_char_lcd;
  inout ps2_mouse_clk;
  inout ps2_mouse_data;
  inout ps2_keyb_clk;
  inout ps2_keyb_data;
  inout iic_scl;
  inout iic_sda;
  output ac97_reset_n;
  input ac97_sdata_In;
  output ac97_sdata_Out;
  output ac97_sync;
  input ac97_bit_clk;
  output phy_rst_n;
  input phy_mii_int_n;
  input phy_col;
  input phy_crs;
  input phy_dv;
  inout phy_mii_clk;
  inout phy_mii_data;
  input phy_rx_clk;
  input [3:0] phy_rx_data;
  input phy_rx_er;
  input phy_tx_clk;
  output [3:0] phy_tx_data;
  output phy_tx_en;
  output phy_tx_er;
  input ddr_clk_fb;
  output [12:0] ddr_ad;
  output [1:0] ddr_ba;
  output ddr_casb;
  output ddr_cke;
  output ddr_clk;
  output ddr_clkb;
  output ddr_csb;
  output [3:0] ddr_dm;
  inout [31:0] ddr_dq;
  inout [3:0] ddr_dqs;
  output ddr_rasb;
  output ddr_web;
  output [5:0] tft_lcd_b;
  output tft_lcd_clk;
  output [5:0] tft_lcd_g;
  output tft_lcd_hsync;
  output [5:0] tft_lcd_r;
  output tft_lcd_vsync;
  output opb_error;
  output plb_error;
  output sram_clk;
  input sram_clk_fb;
  output flash_a23;
  output [22:0] sram_flash_addr;
  inout [31:0] sram_flash_data;
  output sram_cen;
  output sram_flash_oe_n;
  output sram_flash_we_n;
  output [3:0] sram_bw;
  output flash_ce;
  output sram_adv_ld_n;
  output sram_mode;
  input sysace_clk_in;
  input sysace_mpirq;
  output sace_mpce;
  output usb_hpi_reset_n;
  input usb_hpi_int;
  output usb_csn;
  output [6:0] sace_usb_a;
  inout [15:0] sace_usb_d;
  output sace_usb_oen;
  output sace_usb_wen;

  // Internal signals

  wire Dbg_Capture;
  wire Dbg_Clk;
  wire [0:4] Dbg_Reg_En;
  wire Dbg_TDI;
  wire Dbg_TDO;
  wire Dbg_Update;
  wire Debug_Rst;
  wire Ext_BRK;
  wire Ext_NM_BRK;
  wire ac97_bit_clk_BUFGP;
  wire ac97_play_intr;
  wire ac97_record_intr;
  wire ac97_sdata_in_IBUF;
  wire ac97_sdata_out_OBUF;
  wire ac97_sync_OBUF;
  wire [0:31] conn_0_BRAM_Addr;
  wire conn_0_BRAM_Clk;
  wire [0:31] conn_0_BRAM_Din;
  wire [0:31] conn_0_BRAM_Dout;
  wire conn_0_BRAM_EN;
  wire conn_0_BRAM_Rst;
  wire [0:3] conn_0_BRAM_WEN;
  wire [0:31] conn_1_BRAM_Addr;
  wire conn_1_BRAM_Clk;
  wire [0:31] conn_1_BRAM_Din;
  wire [0:31] conn_1_BRAM_Dout;
  wire conn_1_BRAM_EN;
  wire conn_1_BRAM_Rst;
  wire [0:3] conn_1_BRAM_WEN;
  wire dcm_locked;
  wire dcr_clk;
  wire [0:19] dcr_v29_0_DCR_ABus;
  wire dcr_v29_0_DCR_Ack;
  wire [0:31] dcr_v29_0_DCR_M_DBus;
  wire [0:1] dcr_v29_0_DCR_Read;
  wire [0:63] dcr_v29_0_DCR_Sl_DBus;
  wire [0:1] dcr_v29_0_DCR_Write;
  wire [0:9] dcr_v29_0_M_dcrABus;
  wire [0:31] dcr_v29_0_M_dcrDBus;
  wire dcr_v29_0_M_dcrRead;
  wire dcr_v29_0_M_dcrWrite;
  wire [0:1] dcr_v29_0_Sl_dcrAck;
  wire [0:63] dcr_v29_0_Sl_dcrDBus;
  wire [12:0] ddr_ad_OBUF;
  wire [1:0] ddr_ba_OBUF;
  wire ddr_casb_OBUF;
  wire [0:0] ddr_cke_OBUF;
  wire [0:0] ddr_clk_OBUF;
  wire ddr_clk_fb270;
  wire ddr_clk_fb90;
  wire ddr_clk_fb_IBUF;
  wire [0:0] ddr_clkb_OBUF;
  wire [0:0] ddr_csb_OBUF;
  wire [3:0] ddr_dm_OBUF;
  wire [31:0] ddr_dq_I;
  wire [31:0] ddr_dq_O;
  wire [31:0] ddr_dq_T;
  wire [3:0] ddr_dqs_I;
  wire [3:0] ddr_dqs_O;
  wire [3:0] ddr_dqs_T;
  wire ddr_rasb_OBUF;
  wire ddr_web_OBUF;
  wire ext_irq;
  wire flash_a23_OBUF;
  wire flash_ce_OBUF;
  wire flash_oe_n;
  wire [26:0] gpio2_d_out;
  wire [0:26] gpio2_in;
  wire [26:0] gpio2_t_out;
  wire [26:0] gpio_I;
  wire [26:0] gpio_O;
  wire [26:0] gpio_T;
  wire [6:0] gpio_char_lcd_I;
  wire [6:0] gpio_char_lcd_O;
  wire [6:0] gpio_char_lcd_T;
  wire [31:0] gpio_exp_hdr1_I;
  wire [31:0] gpio_exp_hdr1_O;
  wire [31:0] gpio_exp_hdr1_T;
  wire [31:0] gpio_exp_hdr2_I;
  wire [31:0] gpio_exp_hdr2_O;
  wire [31:0] gpio_exp_hdr2_T;
  wire iic_intr;
  wire iic_scl_I;
  wire iic_scl_O;
  wire iic_scl_T;
  wire iic_scl_int_I;
  wire iic_scl_int_O;
  wire iic_scl_int_T;
  wire iic_sda_I;
  wire iic_sda_O;
  wire iic_sda_T;
  wire iic_sda_int_I;
  wire iic_sda_int_O;
  wire iic_sda_int_T;
  wire [0:31] lmb_v10_0_LMB_ABus;
  wire lmb_v10_0_LMB_AddrStrobe;
  wire [0:3] lmb_v10_0_LMB_BE;
  wire [0:31] lmb_v10_0_LMB_ReadDBus;
  wire lmb_v10_0_LMB_ReadStrobe;
  wire lmb_v10_0_LMB_Ready;
  wire [0:31] lmb_v10_0_LMB_WriteDBus;
  wire lmb_v10_0_LMB_WriteStrobe;
  wire [0:31] lmb_v10_0_M_ABus;
  wire lmb_v10_0_M_AddrStrobe;
  wire lmb_v10_0_M_ReadStrobe;
  wire lmb_v10_0_OPB_Rst;
  wire [0:31] lmb_v10_0_Sl_DBus;
  wire [0:0] lmb_v10_0_Sl_Ready;
  wire [0:31] lmb_v10_1_LMB_ABus;
  wire lmb_v10_1_LMB_AddrStrobe;
  wire [0:3] lmb_v10_1_LMB_BE;
  wire [0:31] lmb_v10_1_LMB_ReadDBus;
  wire lmb_v10_1_LMB_ReadStrobe;
  wire lmb_v10_1_LMB_Ready;
  wire [0:31] lmb_v10_1_LMB_WriteDBus;
  wire lmb_v10_1_LMB_WriteStrobe;
  wire [0:31] lmb_v10_1_M_ABus;
  wire lmb_v10_1_M_AddrStrobe;
  wire [0:3] lmb_v10_1_M_BE;
  wire [0:31] lmb_v10_1_M_DBus;
  wire lmb_v10_1_M_ReadStrobe;
  wire lmb_v10_1_M_WriteStrobe;
  wire lmb_v10_1_OPB_Rst;
  wire [0:31] lmb_v10_1_Sl_DBus;
  wire [0:0] lmb_v10_1_Sl_Ready;
  wire mdm_intr;
  wire net_gnd0;
  wire [0:0] net_gnd1;
  wire [0:9] net_gnd10;
  wire [0:15] net_gnd16;
  wire [0:1] net_gnd2;
  wire [0:26] net_gnd27;
  wire [0:31] net_gnd32;
  wire [0:3] net_gnd4;
  wire [0:6] net_gnd7;
  wire net_vcc0;
  wire [0:15] net_vcc16;
  wire [0:1] net_vcc2;
  wire opb_clk;
  wire opb_error_OBUF;
  wire opb_v20_0_Debug_SYS_Rst;
  wire [0:63] opb_v20_0_M_ABus;
  wire [0:7] opb_v20_0_M_BE;
  wire [0:63] opb_v20_0_M_DBus;
  wire [0:1] opb_v20_0_M_RNW;
  wire [0:1] opb_v20_0_M_busLock;
  wire [0:1] opb_v20_0_M_request;
  wire [0:1] opb_v20_0_M_select;
  wire [0:1] opb_v20_0_M_seqAddr;
  wire [0:31] opb_v20_0_OPB_ABus;
  wire [0:3] opb_v20_0_OPB_BE;
  wire [0:31] opb_v20_0_OPB_DBus;
  wire [0:1] opb_v20_0_OPB_MGrant;
  wire opb_v20_0_OPB_RNW;
  wire opb_v20_0_OPB_Rst;
  wire opb_v20_0_OPB_errAck;
  wire opb_v20_0_OPB_retry;
  wire opb_v20_0_OPB_select;
  wire opb_v20_0_OPB_seqAddr;
  wire opb_v20_0_OPB_timeout;
  wire opb_v20_0_OPB_xferAck;
  wire [0:511] opb_v20_0_Sl_DBus;
  wire [0:15] opb_v20_0_Sl_errAck;
  wire [0:15] opb_v20_0_Sl_retry;
  wire [0:15] opb_v20_0_Sl_toutSup;
  wire [0:15] opb_v20_0_Sl_xferAck;
  wire [10:0] pgassign1;
  wire [0:31] pgassign2;
  wire [0:1] pgassign3;
  wire [0:1] pgassign4;
  wire [0:1] pgassign5;
  wire phy_col_IBUF;
  wire phy_crs_IBUF;
  wire phy_dv_IBUF;
  wire phy_mii_clk_I;
  wire phy_mii_clk_O;
  wire phy_mii_clk_T;
  wire phy_mii_data_I;
  wire phy_mii_data_O;
  wire phy_mii_data_T;
  wire phy_mii_int;
  wire phy_mii_int_n_IBUF;
  wire phy_rst_n_OBUF;
  wire phy_rx_clk_BUFGP;
  wire [3:0] phy_rx_data_IBUF;
  wire phy_rx_er_IBUF;
  wire phy_tx_clk_BUFGP;
  wire [3:0] phy_tx_data_OBUF;
  wire phy_tx_en_OBUF;
  wire phy_tx_er_OBUF;
  wire plb_clk;
  wire plb_clk270;
  wire plb_clk90;
  wire plb_clk_n;
  wire plb_error_OBUF;
  wire plb_error_det;
  wire [0:63] plb_v34_0_M_ABus;
  wire [0:15] plb_v34_0_M_BE;
  wire [0:3] plb_v34_0_M_MSize;
  wire [0:1] plb_v34_0_M_RNW;
  wire [0:1] plb_v34_0_M_abort;
  wire [0:1] plb_v34_0_M_busLock;
  wire [0:1] plb_v34_0_M_compress;
  wire [0:1] plb_v34_0_M_guarded;
  wire [0:1] plb_v34_0_M_lockErr;
  wire [0:1] plb_v34_0_M_ordered;
  wire [0:3] plb_v34_0_M_priority;
  wire [0:1] plb_v34_0_M_rdBurst;
  wire [0:1] plb_v34_0_M_request;
  wire [0:7] plb_v34_0_M_size;
  wire [0:5] plb_v34_0_M_type;
  wire [0:1] plb_v34_0_M_wrBurst;
  wire [0:127] plb_v34_0_M_wrDBus;
  wire [0:31] plb_v34_0_PLB_ABus;
  wire [0:7] plb_v34_0_PLB_BE;
  wire [0:1] plb_v34_0_PLB_MAddrAck;
  wire [0:1] plb_v34_0_PLB_MBusy;
  wire [0:1] plb_v34_0_PLB_MErr;
  wire [0:1] plb_v34_0_PLB_MRdBTerm;
  wire [0:1] plb_v34_0_PLB_MRdDAck;
  wire [0:127] plb_v34_0_PLB_MRdDBus;
  wire [0:7] plb_v34_0_PLB_MRdWdAddr;
  wire [0:1] plb_v34_0_PLB_MRearbitrate;
  wire [0:3] plb_v34_0_PLB_MSSize;
  wire [0:1] plb_v34_0_PLB_MSize;
  wire [0:1] plb_v34_0_PLB_MWrBTerm;
  wire [0:1] plb_v34_0_PLB_MWrDAck;
  wire plb_v34_0_PLB_PAValid;
  wire plb_v34_0_PLB_RNW;
  wire plb_v34_0_PLB_Rst;
  wire plb_v34_0_PLB_SAValid;
  wire plb_v34_0_PLB_abort;
  wire plb_v34_0_PLB_busLock;
  wire plb_v34_0_PLB_compress;
  wire plb_v34_0_PLB_guarded;
  wire plb_v34_0_PLB_lockErr;
  wire [0:0] plb_v34_0_PLB_masterID;
  wire plb_v34_0_PLB_ordered;
  wire [0:1] plb_v34_0_PLB_pendPri;
  wire plb_v34_0_PLB_pendReq;
  wire plb_v34_0_PLB_rdBurst;
  wire plb_v34_0_PLB_rdPrim;
  wire [0:1] plb_v34_0_PLB_reqPri;
  wire [0:3] plb_v34_0_PLB_size;
  wire [0:2] plb_v34_0_PLB_type;
  wire plb_v34_0_PLB_wrBurst;
  wire [0:63] plb_v34_0_PLB_wrDBus;
  wire plb_v34_0_PLB_wrPrim;
  wire [0:1] plb_v34_0_Sl_MBusy;
  wire [0:1] plb_v34_0_Sl_MErr;
  wire [0:1] plb_v34_0_Sl_SSize;
  wire [0:0] plb_v34_0_Sl_addrAck;
  wire [0:0] plb_v34_0_Sl_rdBTerm;
  wire [0:0] plb_v34_0_Sl_rdComp;
  wire [0:0] plb_v34_0_Sl_rdDAck;
  wire [0:63] plb_v34_0_Sl_rdDBus;
  wire [0:3] plb_v34_0_Sl_rdWdAddr;
  wire [0:0] plb_v34_0_Sl_rearbitrate;
  wire [0:0] plb_v34_0_Sl_wait;
  wire [0:0] plb_v34_0_Sl_wrBTerm;
  wire [0:0] plb_v34_0_Sl_wrComp;
  wire [0:0] plb_v34_0_Sl_wrDAck;
  wire ps2_1_intr;
  wire ps2_2_intr;
  wire ps2_clk_rx_1;
  wire ps2_clk_rx_2;
  wire ps2_clk_tx_1;
  wire ps2_clk_tx_2;
  wire ps2_d_rx_1;
  wire ps2_d_rx_2;
  wire ps2_d_tx_1;
  wire ps2_d_tx_2;
  wire ps2_keyb_clk_I;
  wire ps2_keyb_clk_O;
  wire ps2_keyb_clk_T;
  wire ps2_keyb_data_I;
  wire ps2_keyb_data_O;
  wire ps2_keyb_data_T;
  wire ps2_mouse_clk_I;
  wire ps2_mouse_clk_O;
  wire ps2_mouse_clk_T;
  wire ps2_mouse_data_I;
  wire ps2_mouse_data_O;
  wire ps2_mouse_data_T;
  wire sace_mpce_OBUF;
  wire [6:0] sace_usb_a_OBUF;
  wire [15:0] sace_usb_d_I;
  wire [15:0] sace_usb_d_O;
  wire [15:0] sace_usb_d_T;
  wire sace_usb_oen_OBUF;
  wire sace_usb_wen_OBUF;
  wire sram_adv_ld_n_OBUF;
  wire [3:0] sram_bw_OBUF;
  wire sram_cen_OBUF;
  wire sram_clk_OBUF;
  wire sram_clk_fb_IBUF;
  wire [22:0] sram_flash_addr_OBUF;
  wire [31:0] sram_flash_data_I;
  wire [31:0] sram_flash_data_O;
  wire [31:0] sram_flash_data_T;
  wire sram_flash_oe_n_OBUF;
  wire sram_flash_we_n_OBUF;
  wire sram_mode_OBUF;
  wire sram_oe_n;
  wire sys_clk_in_IBUF;
  wire [0:0] sys_rst;
  wire sys_rst_in_IBUF;
  wire sys_rst_in_i;
  wire sys_rst_n;
  wire sysace_clk_in_BUFGP;
  wire sysace_intr;
  wire [6:0] sysace_mpa;
  wire [15:0] sysace_mpd_i;
  wire [15:0] sysace_mpd_o;
  wire [15:0] sysace_mpd_t;
  wire sysace_mpirq_IBUF;
  wire sysace_mpoe;
  wire sysace_mpwe;
  wire tft_clk;
  wire [5:0] tft_lcd_b_OBUF;
  wire tft_lcd_clk_OBUF;
  wire [5:0] tft_lcd_g_OBUF;
  wire tft_lcd_hsync_OBUF;
  wire [5:0] tft_lcd_r_OBUF;
  wire tft_lcd_vsync_OBUF;
  wire timer_intr;
  wire uart_RX_IBUF;
  wire uart_TX_OBUF;
  wire uart_intr;
  wire [0:31] usb_addr;
  wire [0:0] usb_ce;
  wire [0:0] usb_csn_OBUF;
  wire [0:31] usb_data_i;
  wire [0:31] usb_data_o;
  wire [0:31] usb_data_t;
  wire usb_hpi_int_IBUF;
  wire usb_hpi_reset_n_OBUF;
  wire [0:0] usb_rdn;
  wire usb_wrn;

  // Internal assignments

  assign pgassign1[10] = mdm_intr;
  assign pgassign1[9] = uart_intr;
  assign pgassign1[8] = ps2_1_intr;
  assign pgassign1[7] = ps2_2_intr;
  assign pgassign1[6] = iic_intr;
  assign pgassign1[5] = ac97_play_intr;
  assign pgassign1[4] = ac97_record_intr;
  assign pgassign1[3] = sysace_intr;
  assign pgassign1[2] = phy_mii_int;
  assign pgassign1[1] = timer_intr;
  assign pgassign1[0] = usb_hpi_int_IBUF;
  assign flash_a23_OBUF = pgassign2[6];
  assign sram_flash_addr_OBUF[22:0] = pgassign2[7:29];
  assign sram_cen_OBUF = pgassign3[0];
  assign sram_oe_n = pgassign4[0];
  assign flash_oe_n = pgassign4[1];
  assign flash_ce_OBUF = pgassign5[1];
  assign net_gnd0 = 1'b0;
  assign net_gnd1[0:0] = 1'b0;
  assign net_gnd10[0:9] = 10'b0000000000;
  assign net_gnd16[0:15] = 16'b0000000000000000;
  assign net_gnd2[0:1] = 2'b00;
  assign net_gnd27[0:26] = 27'b000000000000000000000000000;
  assign net_gnd32[0:31] = 32'b00000000000000000000000000000000;
  assign net_gnd4[0:3] = 4'b0000;
  assign net_gnd7[0:6] = 7'b0000000;
  assign net_vcc0 = 1'b1;
  assign net_vcc16[0:15] = 16'b1111111111111111;
  assign net_vcc2[0:1] = 2'b11;

  proc_sys_reset_0_wrapper
    proc_sys_reset_0 (
      .Slowest_sync_clk ( opb_clk ),
      .Ext_Reset_In ( sys_rst_in_i ),
      .Aux_Reset_In ( net_gnd0 ),
      .Core_Reset_Req ( net_gnd0 ),
      .Chip_Reset_Req ( net_gnd0 ),
      .System_Reset_Req ( net_gnd0 ),
      .Dcm_locked ( dcm_locked ),
      .Rstc405resetcore (  ),
      .Rstc405resetchip (  ),
      .Rstc405resetsys (  ),
      .Bus_Struct_Reset ( sys_rst[0:0] ),
      .Peripheral_Reset (  )
    );

  clocks_0_wrapper
    clocks_0 (
      .sys_clk ( sys_clk_in_IBUF ),
      .sysace_clk ( sysace_clk_in_BUFGP ),
      .tft_clk ( tft_clk ),
      .dcm_rst_n ( sys_rst_in_i ),
      .plb_clk ( plb_clk ),
      .plb_clk_n ( plb_clk_n ),
      .plb_clk90 ( plb_clk90 ),
      .plb_clk270 ( plb_clk270 ),
      .opb_clk ( opb_clk ),
      .dcr_clk ( dcr_clk ),
      .ddr_fb_clk ( ddr_clk_fb_IBUF ),
      .ddr_fb_clk90 ( ddr_clk_fb90 ),
      .ddr_fb_clk270 ( ddr_clk_fb270 ),
      .dcm_locked ( dcm_locked ),
      .sram_clk ( sram_clk_OBUF ),
      .sram_clk_fb ( sram_clk_fb_IBUF )
    );

  misc_logic_0_wrapper
    misc_logic_0 (
      .rst_n ( sys_rst_n ),
      .rst ( sys_rst[0] ),
      .sys_rst_in ( sys_rst_in_IBUF ),
      .sys_rst_in_i ( sys_rst_in_i ),
      .clk ( plb_clk ),
      .plb_arb_error ( plb_error_det ),
      .opb_error ( opb_error_OBUF ),
      .plb_error ( plb_error_OBUF ),
      .OPB_xferAck ( opb_v20_0_OPB_xferAck ),
      .OPB_retry ( opb_v20_0_OPB_retry ),
      .OPB_errAck ( opb_v20_0_OPB_errAck ),
      .OPB_timeout ( opb_v20_0_OPB_timeout ),
      .phy_mii_int_n ( phy_mii_int_n_IBUF ),
      .phy_mii_int ( phy_mii_int ),
      .ps2_clk_rx_1 ( ps2_clk_rx_1 ),
      .ps2_clk_rx_2 ( ps2_clk_rx_2 ),
      .ps2_clk_tx_1 ( ps2_clk_tx_1 ),
      .ps2_clk_tx_2 ( ps2_clk_tx_2 ),
      .ps2_d_rx_1 ( ps2_d_rx_1 ),
      .ps2_d_rx_2 ( ps2_d_rx_2 ),
      .ps2_d_tx_1 ( ps2_d_tx_1 ),
      .ps2_d_tx_2 ( ps2_d_tx_2 ),
      .sram_oe_n ( sram_oe_n ),
      .flash_oe_n ( flash_oe_n ),
      .sram_flash_oe_n ( sram_flash_oe_n_OBUF ),
      .usb_hpi_reset_n ( usb_hpi_reset_n_OBUF ),
      .GPIO2_d_out ( gpio2_d_out ),
      .GPIO2_t_out ( gpio2_t_out ),
      .GPIO2_in ( gpio2_in[0:26] ),
      .iic_scl_int_i ( iic_scl_int_I ),
      .iic_scl_int_o ( iic_scl_int_O ),
      .iic_scl_int_t ( iic_scl_int_T ),
      .iic_sda_int_i ( iic_sda_int_I ),
      .iic_sda_int_o ( iic_sda_int_O ),
      .iic_sda_int_t ( iic_sda_int_T ),
      .usb_addr ( usb_addr ),
      .usb_data_i ( usb_data_i ),
      .usb_data_o ( usb_data_o ),
      .usb_data_t ( usb_data_t ),
      .usb_rdn ( usb_rdn[0] ),
      .usb_wrn ( usb_wrn ),
      .usb_ce ( usb_ce[0] ),
      .sysace_mpa ( sysace_mpa ),
      .sysace_mpd_i ( sysace_mpd_i ),
      .sysace_mpd_o ( sysace_mpd_o ),
      .sysace_mpd_t ( sysace_mpd_t ),
      .sysace_mpoe ( sysace_mpoe ),
      .sysace_mpwe ( sysace_mpwe ),
      .sace_usb_a ( sace_usb_a_OBUF ),
      .sace_usb_oen ( sace_usb_oen_OBUF ),
      .sace_usb_wen ( sace_usb_wen_OBUF ),
      .ps2_mouse_clk_I ( ps2_mouse_clk_I ),
      .ps2_mouse_clk_O ( ps2_mouse_clk_O ),
      .ps2_mouse_clk_T ( ps2_mouse_clk_T ),
      .ps2_mouse_data_I ( ps2_mouse_data_I ),
      .ps2_mouse_data_O ( ps2_mouse_data_O ),
      .ps2_mouse_data_T ( ps2_mouse_data_T ),
      .ps2_keyb_clk_I ( ps2_keyb_clk_I ),
      .ps2_keyb_clk_O ( ps2_keyb_clk_O ),
      .ps2_keyb_clk_T ( ps2_keyb_clk_T ),
      .ps2_keyb_data_I ( ps2_keyb_data_I ),
      .ps2_keyb_data_O ( ps2_keyb_data_O ),
      .ps2_keyb_data_T ( ps2_keyb_data_T ),
      .sda_I ( iic_sda_I ),
      .sda_O ( iic_sda_O ),
      .sda_T ( iic_sda_T ),
      .scl_I ( iic_scl_I ),
      .scl_O ( iic_scl_O ),
      .scl_T ( iic_scl_T ),
      .sace_usb_d_I ( sace_usb_d_I ),
      .sace_usb_d_O ( sace_usb_d_O ),
      .sace_usb_d_T ( sace_usb_d_T )
    );

  microblaze_0_wrapper
    microblaze_0 (
      .CLK ( opb_clk ),
      .RESET ( opb_v20_0_OPB_Rst ),
      .INTERRUPT ( ext_irq ),
      .DEBUG_RST ( Debug_Rst ),
      .EXT_BRK ( Ext_BRK ),
      .EXT_NM_BRK ( Ext_NM_BRK ),
      .DBG_STOP ( net_gnd0 ),
      .INSTR ( lmb_v10_0_LMB_ReadDBus ),
      .I_ADDRTAG (  ),
      .IREADY ( lmb_v10_0_LMB_Ready ),
      .IWAIT ( net_gnd0 ),
      .INSTR_ADDR ( lmb_v10_0_M_ABus ),
      .IFETCH ( lmb_v10_0_M_ReadStrobe ),
      .I_AS ( lmb_v10_0_M_AddrStrobe ),
      .DATA_READ ( lmb_v10_1_LMB_ReadDBus ),
      .DREADY ( lmb_v10_1_LMB_Ready ),
      .DWAIT ( net_gnd0 ),
      .DATA_WRITE ( lmb_v10_1_M_DBus ),
      .DATA_ADDR ( lmb_v10_1_M_ABus ),
      .D_ADDRTAG (  ),
      .D_AS ( lmb_v10_1_M_AddrStrobe ),
      .READ_STROBE ( lmb_v10_1_M_ReadStrobe ),
      .WRITE_STROBE ( lmb_v10_1_M_WriteStrobe ),
      .BYTE_ENABLE ( lmb_v10_1_M_BE ),
      .DM_ABUS ( opb_v20_0_M_ABus[0:31] ),
      .DM_BE ( opb_v20_0_M_BE[0:3] ),
      .DM_BUSLOCK ( opb_v20_0_M_busLock[0] ),
      .DM_DBUS ( opb_v20_0_M_DBus[0:31] ),
      .DM_REQUEST ( opb_v20_0_M_request[0] ),
      .DM_RNW ( opb_v20_0_M_RNW[0] ),
      .DM_SELECT ( opb_v20_0_M_select[0] ),
      .DM_SEQADDR ( opb_v20_0_M_seqAddr[0] ),
      .DOPB_DBUS ( opb_v20_0_OPB_DBus ),
      .DOPB_ERRACK ( opb_v20_0_OPB_errAck ),
      .DOPB_MGRANT ( opb_v20_0_OPB_MGrant[0] ),
      .DOPB_RETRY ( opb_v20_0_OPB_retry ),
      .DOPB_TIMEOUT ( opb_v20_0_OPB_timeout ),
      .DOPB_XFERACK ( opb_v20_0_OPB_xferAck ),
      .IM_ABUS ( opb_v20_0_M_ABus[32:63] ),
      .IM_BE ( opb_v20_0_M_BE[4:7] ),
      .IM_BUSLOCK ( opb_v20_0_M_busLock[1] ),
      .IM_DBUS ( opb_v20_0_M_DBus[32:63] ),
      .IM_REQUEST ( opb_v20_0_M_request[1] ),
      .IM_RNW ( opb_v20_0_M_RNW[1] ),
      .IM_SELECT ( opb_v20_0_M_select[1] ),
      .IM_SEQADDR ( opb_v20_0_M_seqAddr[1] ),
      .IOPB_DBUS ( opb_v20_0_OPB_DBus ),
      .IOPB_ERRACK ( opb_v20_0_OPB_errAck ),
      .IOPB_MGRANT ( opb_v20_0_OPB_MGrant[1] ),
      .IOPB_RETRY ( opb_v20_0_OPB_retry ),
      .IOPB_TIMEOUT ( opb_v20_0_OPB_timeout ),
      .IOPB_XFERACK ( opb_v20_0_OPB_xferAck ),
      .DBG_CLK ( Dbg_Clk ),
      .DBG_TDI ( Dbg_TDI ),
      .DBG_TDO ( Dbg_TDO ),
      .DBG_REG_EN ( Dbg_Reg_En ),
      .DBG_CAPTURE ( Dbg_Capture ),
      .DBG_UPDATE ( Dbg_Update ),
      .VALID_INSTR (  ),
      .PC_EX (  ),
      .REG_WRITE (  ),
      .REG_ADDR (  ),
      .MSR_REG (  ),
      .NEW_REG_VALUE (  ),
      .PIPE_RUNNING (  ),
      .INTERRUPT_TAKEN (  ),
      .JUMP_TAKEN (  ),
      .PREFETCH_ADDR (  ),
      .MB_Halted (  ),
      .Trace_Branch_Instr (  ),
      .Trace_Delay_Slot (  ),
      .Trace_Data_Address (  ),
      .Trace_AS (  ),
      .Trace_Data_Read (  ),
      .Trace_Data_Write (  ),
      .Trace_DCache_Req (  ),
      .Trace_DCache_Hit (  ),
      .Trace_ICache_Req (  ),
      .Trace_ICache_Hit (  ),
      .Trace_Instr_EX (  ),
      .FSL0_S_CLK (  ),
      .FSL0_S_READ (  ),
      .FSL0_S_DATA ( net_gnd32 ),
      .FSL0_S_CONTROL ( net_gnd0 ),
      .FSL0_S_EXISTS ( net_gnd0 ),
      .FSL0_M_CLK (  ),
      .FSL0_M_WRITE (  ),
      .FSL0_M_DATA (  ),
      .FSL0_M_CONTROL (  ),
      .FSL0_M_FULL ( net_gnd0 ),
      .FSL1_S_CLK (  ),
      .FSL1_S_READ (  ),
      .FSL1_S_DATA ( net_gnd32 ),
      .FSL1_S_CONTROL ( net_gnd0 ),
      .FSL1_S_EXISTS ( net_gnd0 ),
      .FSL1_M_CLK (  ),
      .FSL1_M_WRITE (  ),
      .FSL1_M_DATA (  ),
      .FSL1_M_CONTROL (  ),
      .FSL1_M_FULL ( net_gnd0 ),
      .FSL2_S_CLK (  ),
      .FSL2_S_READ (  ),
      .FSL2_S_DATA ( net_gnd32 ),
      .FSL2_S_CONTROL ( net_gnd0 ),
      .FSL2_S_EXISTS ( net_gnd0 ),
      .FSL2_M_CLK (  ),
      .FSL2_M_WRITE (  ),
      .FSL2_M_DATA (  ),
      .FSL2_M_CONTROL (  ),
      .FSL2_M_FULL ( net_gnd0 ),
      .FSL3_S_CLK (  ),
      .FSL3_S_READ (  ),
      .FSL3_S_DATA ( net_gnd32 ),
      .FSL3_S_CONTROL ( net_gnd0 ),
      .FSL3_S_EXISTS ( net_gnd0 ),
      .FSL3_M_CLK (  ),
      .FSL3_M_WRITE (  ),
      .FSL3_M_DATA (  ),
      .FSL3_M_CONTROL (  ),
      .FSL3_M_FULL ( net_gnd0 ),
      .FSL4_S_CLK (  ),
      .FSL4_S_READ (  ),
      .FSL4_S_DATA ( net_gnd32 ),
      .FSL4_S_CONTROL ( net_gnd0 ),
      .FSL4_S_EXISTS ( net_gnd0 ),
      .FSL4_M_CLK (  ),
      .FSL4_M_WRITE (  ),
      .FSL4_M_DATA (  ),
      .FSL4_M_CONTROL (  ),
      .FSL4_M_FULL ( net_gnd0 ),
      .FSL5_S_CLK (  ),
      .FSL5_S_READ (  ),
      .FSL5_S_DATA ( net_gnd32 ),
      .FSL5_S_CONTROL ( net_gnd0 ),
      .FSL5_S_EXISTS ( net_gnd0 ),
      .FSL5_M_CLK (  ),
      .FSL5_M_WRITE (  ),
      .FSL5_M_DATA (  ),
      .FSL5_M_CONTROL (  ),
      .FSL5_M_FULL ( net_gnd0 ),
      .FSL6_S_CLK (  ),
      .FSL6_S_READ (  ),
      .FSL6_S_DATA ( net_gnd32 ),
      .FSL6_S_CONTROL ( net_gnd0 ),
      .FSL6_S_EXISTS ( net_gnd0 ),
      .FSL6_M_CLK (  ),
      .FSL6_M_WRITE (  ),
      .FSL6_M_DATA (  ),
      .FSL6_M_CONTROL (  ),
      .FSL6_M_FULL ( net_gnd0 ),
      .FSL7_S_CLK (  ),
      .FSL7_S_READ (  ),
      .FSL7_S_DATA ( net_gnd32 ),
      .FSL7_S_CONTROL ( net_gnd0 ),
      .FSL7_S_EXISTS ( net_gnd0 ),
      .FSL7_M_CLK (  ),
      .FSL7_M_WRITE (  ),
      .FSL7_M_DATA (  ),
      .FSL7_M_CONTROL (  ),
      .FSL7_M_FULL ( net_gnd0 )
    );

  lmb_bram_if_cntlr_0_wrapper
    lmb_bram_if_cntlr_0 (
      .LMB_Clk ( opb_clk ),
      .LMB_Rst ( lmb_v10_1_OPB_Rst ),
      .LMB_ABus ( lmb_v10_1_LMB_ABus ),
      .LMB_WriteDBus ( lmb_v10_1_LMB_WriteDBus ),
      .LMB_AddrStrobe ( lmb_v10_1_LMB_AddrStrobe ),
      .LMB_ReadStrobe ( lmb_v10_1_LMB_ReadStrobe ),
      .LMB_WriteStrobe ( lmb_v10_1_LMB_WriteStrobe ),
      .LMB_BE ( lmb_v10_1_LMB_BE ),
      .Sl_DBus ( lmb_v10_1_Sl_DBus ),
      .Sl_Ready ( lmb_v10_1_Sl_Ready[0] ),
      .BRAM_Rst_A ( conn_0_BRAM_Rst ),
      .BRAM_Clk_A ( conn_0_BRAM_Clk ),
      .BRAM_EN_A ( conn_0_BRAM_EN ),
      .BRAM_WEN_A ( conn_0_BRAM_WEN ),
      .BRAM_Addr_A ( conn_0_BRAM_Addr ),
      .BRAM_Din_A ( conn_0_BRAM_Din ),
      .BRAM_Dout_A ( conn_0_BRAM_Dout )
    );

  lmb_v10_0_wrapper
    lmb_v10_0 (
      .LMB_Clk ( opb_clk ),
      .SYS_Rst ( sys_rst[0] ),
      .LMB_Rst ( lmb_v10_0_OPB_Rst ),
      .M_ABus ( lmb_v10_0_M_ABus ),
      .M_ReadStrobe ( lmb_v10_0_M_ReadStrobe ),
      .M_WriteStrobe ( net_gnd0 ),
      .M_AddrStrobe ( lmb_v10_0_M_AddrStrobe ),
      .M_DBus ( net_gnd32 ),
      .M_BE ( net_gnd4 ),
      .Sl_DBus ( lmb_v10_0_Sl_DBus ),
      .Sl_Ready ( lmb_v10_0_Sl_Ready[0:0] ),
      .LMB_ABus ( lmb_v10_0_LMB_ABus ),
      .LMB_ReadStrobe ( lmb_v10_0_LMB_ReadStrobe ),
      .LMB_WriteStrobe ( lmb_v10_0_LMB_WriteStrobe ),
      .LMB_AddrStrobe ( lmb_v10_0_LMB_AddrStrobe ),
      .LMB_ReadDBus ( lmb_v10_0_LMB_ReadDBus ),
      .LMB_WriteDBus ( lmb_v10_0_LMB_WriteDBus ),
      .LMB_Ready ( lmb_v10_0_LMB_Ready ),
      .LMB_BE ( lmb_v10_0_LMB_BE )
    );

  lmb_bram_if_cntlr_1_wrapper
    lmb_bram_if_cntlr_1 (
      .LMB_Clk ( opb_clk ),
      .LMB_Rst ( lmb_v10_0_OPB_Rst ),
      .LMB_ABus ( lmb_v10_0_LMB_ABus ),
      .LMB_WriteDBus ( lmb_v10_0_LMB_WriteDBus ),
      .LMB_AddrStrobe ( lmb_v10_0_LMB_AddrStrobe ),
      .LMB_ReadStrobe ( lmb_v10_0_LMB_ReadStrobe ),
      .LMB_WriteStrobe ( lmb_v10_0_LMB_WriteStrobe ),
      .LMB_BE ( lmb_v10_0_LMB_BE ),
      .Sl_DBus ( lmb_v10_0_Sl_DBus ),
      .Sl_Ready ( lmb_v10_0_Sl_Ready[0] ),
      .BRAM_Rst_A ( conn_1_BRAM_Rst ),
      .BRAM_Clk_A ( conn_1_BRAM_Clk ),
      .BRAM_EN_A ( conn_1_BRAM_EN ),
      .BRAM_WEN_A ( conn_1_BRAM_WEN ),
      .BRAM_Addr_A ( conn_1_BRAM_Addr ),
      .BRAM_Din_A ( conn_1_BRAM_Din ),
      .BRAM_Dout_A ( conn_1_BRAM_Dout )
    );

  lmb_v10_1_wrapper
    lmb_v10_1 (
      .LMB_Clk ( opb_clk ),
      .SYS_Rst ( sys_rst[0] ),
      .LMB_Rst ( lmb_v10_1_OPB_Rst ),
      .M_ABus ( lmb_v10_1_M_ABus ),
      .M_ReadStrobe ( lmb_v10_1_M_ReadStrobe ),
      .M_WriteStrobe ( lmb_v10_1_M_WriteStrobe ),
      .M_AddrStrobe ( lmb_v10_1_M_AddrStrobe ),
      .M_DBus ( lmb_v10_1_M_DBus ),
      .M_BE ( lmb_v10_1_M_BE ),
      .Sl_DBus ( lmb_v10_1_Sl_DBus ),
      .Sl_Ready ( lmb_v10_1_Sl_Ready[0:0] ),
      .LMB_ABus ( lmb_v10_1_LMB_ABus ),
      .LMB_ReadStrobe ( lmb_v10_1_LMB_ReadStrobe ),
      .LMB_WriteStrobe ( lmb_v10_1_LMB_WriteStrobe ),
      .LMB_AddrStrobe ( lmb_v10_1_LMB_AddrStrobe ),
      .LMB_ReadDBus ( lmb_v10_1_LMB_ReadDBus ),
      .LMB_WriteDBus ( lmb_v10_1_LMB_WriteDBus ),
      .LMB_Ready ( lmb_v10_1_LMB_Ready ),
      .LMB_BE ( lmb_v10_1_LMB_BE )
    );

  bram_block_0_wrapper
    bram_block_0 (
      .BRAM_Rst_A ( conn_0_BRAM_Rst ),
      .BRAM_Clk_A ( conn_0_BRAM_Clk ),
      .BRAM_EN_A ( conn_0_BRAM_EN ),
      .BRAM_WEN_A ( conn_0_BRAM_WEN ),
      .BRAM_Addr_A ( conn_0_BRAM_Addr ),
      .BRAM_Din_A ( conn_0_BRAM_Din ),
      .BRAM_Dout_A ( conn_0_BRAM_Dout ),
      .BRAM_Rst_B ( conn_1_BRAM_Rst ),
      .BRAM_Clk_B ( conn_1_BRAM_Clk ),
      .BRAM_EN_B ( conn_1_BRAM_EN ),
      .BRAM_WEN_B ( conn_1_BRAM_WEN ),
      .BRAM_Addr_B ( conn_1_BRAM_Addr ),
      .BRAM_Din_B ( conn_1_BRAM_Din ),
      .BRAM_Dout_B ( conn_1_BRAM_Dout )
    );

  opb_v20_0_wrapper
    opb_v20_0 (
      .OPB_Clk ( opb_clk ),
      .OPB_Rst ( opb_v20_0_OPB_Rst ),
      .SYS_Rst ( sys_rst[0] ),
      .Debug_SYS_Rst ( opb_v20_0_Debug_SYS_Rst ),
      .WDT_Rst ( net_gnd0 ),
      .M_ABus ( opb_v20_0_M_ABus ),
      .M_BE ( opb_v20_0_M_BE ),
      .M_beXfer ( net_gnd2 ),
      .M_busLock ( opb_v20_0_M_busLock ),
      .M_DBus ( opb_v20_0_M_DBus ),
      .M_DBusEn ( net_gnd2 ),
      .M_DBusEn32_63 ( net_vcc2 ),
      .M_dwXfer ( net_gnd2 ),
      .M_fwXfer ( net_gnd2 ),
      .M_hwXfer ( net_gnd2 ),
      .M_request ( opb_v20_0_M_request ),
      .M_RNW ( opb_v20_0_M_RNW ),
      .M_select ( opb_v20_0_M_select ),
      .M_seqAddr ( opb_v20_0_M_seqAddr ),
      .Sl_beAck ( net_gnd16 ),
      .Sl_DBus ( opb_v20_0_Sl_DBus ),
      .Sl_DBusEn ( net_vcc16 ),
      .Sl_DBusEn32_63 ( net_vcc16 ),
      .Sl_errAck ( opb_v20_0_Sl_errAck ),
      .Sl_dwAck ( net_gnd16 ),
      .Sl_fwAck ( net_gnd16 ),
      .Sl_hwAck ( net_gnd16 ),
      .Sl_retry ( opb_v20_0_Sl_retry ),
      .Sl_toutSup ( opb_v20_0_Sl_toutSup ),
      .Sl_xferAck ( opb_v20_0_Sl_xferAck ),
      .OPB_MRequest (  ),
      .OPB_ABus ( opb_v20_0_OPB_ABus ),
      .OPB_BE ( opb_v20_0_OPB_BE ),
      .OPB_beXfer (  ),
      .OPB_beAck (  ),
      .OPB_busLock (  ),
      .OPB_rdDBus (  ),
      .OPB_wrDBus (  ),
      .OPB_DBus ( opb_v20_0_OPB_DBus ),
      .OPB_errAck ( opb_v20_0_OPB_errAck ),
      .OPB_dwAck (  ),
      .OPB_dwXfer (  ),
      .OPB_fwAck (  ),
      .OPB_fwXfer (  ),
      .OPB_hwAck (  ),
      .OPB_hwXfer (  ),
      .OPB_MGrant ( opb_v20_0_OPB_MGrant ),
      .OPB_pendReq (  ),
      .OPB_retry ( opb_v20_0_OPB_retry ),
      .OPB_RNW ( opb_v20_0_OPB_RNW ),
      .OPB_select ( opb_v20_0_OPB_select ),
      .OPB_seqAddr ( opb_v20_0_OPB_seqAddr ),
      .OPB_timeout ( opb_v20_0_OPB_timeout ),
      .OPB_toutSup (  ),
      .OPB_xferAck ( opb_v20_0_OPB_xferAck )
    );

  opb_mdm_0_wrapper
    opb_mdm_0 (
      .OPB_Clk ( opb_clk ),
      .OPB_Rst ( opb_v20_0_OPB_Rst ),
      .Interrupt ( mdm_intr ),
      .Debug_SYS_Rst ( opb_v20_0_Debug_SYS_Rst ),
      .Debug_Rst ( Debug_Rst ),
      .Ext_BRK ( Ext_BRK ),
      .Ext_NM_BRK ( Ext_NM_BRK ),
      .OPB_ABus ( opb_v20_0_OPB_ABus ),
      .OPB_BE ( opb_v20_0_OPB_BE ),
      .OPB_RNW ( opb_v20_0_OPB_RNW ),
      .OPB_select ( opb_v20_0_OPB_select ),
      .OPB_seqAddr ( opb_v20_0_OPB_seqAddr ),
      .OPB_DBus ( opb_v20_0_OPB_DBus ),
      .MDM_DBus ( opb_v20_0_Sl_DBus[0:31] ),
      .MDM_errAck ( opb_v20_0_Sl_errAck[0] ),
      .MDM_retry ( opb_v20_0_Sl_retry[0] ),
      .MDM_toutSup ( opb_v20_0_Sl_toutSup[0] ),
      .MDM_xferAck ( opb_v20_0_Sl_xferAck[0] ),
      .Dbg_Clk_0 ( Dbg_Clk ),
      .Dbg_TDI_0 ( Dbg_TDI ),
      .Dbg_TDO_0 ( Dbg_TDO ),
      .Dbg_Reg_En_0 ( Dbg_Reg_En ),
      .Dbg_Capture_0 ( Dbg_Capture ),
      .Dbg_Update_0 ( Dbg_Update ),
      .Dbg_Clk_1 (  ),
      .Dbg_TDI_1 (  ),
      .Dbg_TDO_1 ( net_gnd0 ),
      .Dbg_Reg_En_1 (  ),
      .Dbg_Capture_1 (  ),
      .Dbg_Update_1 (  ),
      .Dbg_Clk_2 (  ),
      .Dbg_TDI_2 (  ),
      .Dbg_TDO_2 ( net_gnd0 ),
      .Dbg_Reg_En_2 (  ),
      .Dbg_Capture_2 (  ),
      .Dbg_Update_2 (  ),
      .Dbg_Clk_3 (  ),
      .Dbg_TDI_3 (  ),
      .Dbg_TDO_3 ( net_gnd0 ),
      .Dbg_Reg_En_3 (  ),
      .Dbg_Capture_3 (  ),
      .Dbg_Update_3 (  ),
      .Dbg_Clk_4 (  ),
      .Dbg_TDI_4 (  ),
      .Dbg_TDO_4 ( net_gnd0 ),
      .Dbg_Reg_En_4 (  ),
      .Dbg_Capture_4 (  ),
      .Dbg_Update_4 (  ),
      .Dbg_Clk_5 (  ),
      .Dbg_TDI_5 (  ),
      .Dbg_TDO_5 ( net_gnd0 ),
      .Dbg_Reg_En_5 (  ),
      .Dbg_Capture_5 (  ),
      .Dbg_Update_5 (  ),
      .Dbg_Clk_6 (  ),
      .Dbg_TDI_6 (  ),
      .Dbg_TDO_6 ( net_gnd0 ),
      .Dbg_Reg_En_6 (  ),
      .Dbg_Capture_6 (  ),
      .Dbg_Update_6 (  ),
      .Dbg_Clk_7 (  ),
      .Dbg_TDI_7 (  ),
      .Dbg_TDO_7 ( net_gnd0 ),
      .Dbg_Reg_En_7 (  ),
      .Dbg_Capture_7 (  ),
      .Dbg_Update_7 (  ),
      .bscan_tdi (  ),
      .bscan_reset (  ),
      .bscan_shift (  ),
      .bscan_update (  ),
      .bscan_capture (  ),
      .bscan_sel1 (  ),
      .bscan_drck1 (  ),
      .bscan_tdo1 ( net_gnd0 ),
      .FSL0_S_CLK (  ),
      .FSL0_S_READ (  ),
      .FSL0_S_DATA ( net_gnd32 ),
      .FSL0_S_CONTROL ( net_gnd0 ),
      .FSL0_S_EXISTS ( net_gnd0 ),
      .FSL0_M_CLK (  ),
      .FSL0_M_WRITE (  ),
      .FSL0_M_DATA (  ),
      .FSL0_M_CONTROL (  ),
      .FSL0_M_FULL ( net_gnd0 )
    );

  opb_intc_0_wrapper
    opb_intc_0 (
      .OPB_Clk ( opb_clk ),
      .Intr ( pgassign1 ),
      .OPB_Rst ( opb_v20_0_OPB_Rst ),
      .OPB_ABus ( opb_v20_0_OPB_ABus ),
      .OPB_BE ( opb_v20_0_OPB_BE ),
      .OPB_RNW ( opb_v20_0_OPB_RNW ),
      .OPB_select ( opb_v20_0_OPB_select ),
      .OPB_seqAddr ( opb_v20_0_OPB_seqAddr ),
      .OPB_DBus ( opb_v20_0_OPB_DBus ),
      .IntC_DBus ( opb_v20_0_Sl_DBus[32:63] ),
      .IntC_errAck ( opb_v20_0_Sl_errAck[1] ),
      .IntC_retry ( opb_v20_0_Sl_retry[1] ),
      .IntC_toutSup ( opb_v20_0_Sl_toutSup[1] ),
      .IntC_xferAck ( opb_v20_0_Sl_xferAck[1] ),
      .Irq ( ext_irq )
    );

  opb_timer_0_wrapper
    opb_timer_0 (
      .OPB_Clk ( opb_clk ),
      .OPB_Rst ( opb_v20_0_OPB_Rst ),
      .OPB_ABus ( opb_v20_0_OPB_ABus ),
      .OPB_BE ( opb_v20_0_OPB_BE ),
      .OPB_DBus ( opb_v20_0_OPB_DBus ),
      .OPB_RNW ( opb_v20_0_OPB_RNW ),
      .OPB_select ( opb_v20_0_OPB_select ),
      .OPB_seqAddr ( opb_v20_0_OPB_seqAddr ),
      .TC_DBus ( opb_v20_0_Sl_DBus[64:95] ),
      .TC_errAck ( opb_v20_0_Sl_errAck[2] ),
      .TC_retry ( opb_v20_0_Sl_retry[2] ),
      .TC_toutSup ( opb_v20_0_Sl_toutSup[2] ),
      .TC_xferAck ( opb_v20_0_Sl_xferAck[2] ),
      .CaptureTrig0 ( net_gnd0 ),
      .CaptureTrig1 ( net_gnd0 ),
      .GenerateOut0 (  ),
      .GenerateOut1 (  ),
      .PWM0 (  ),
      .Interrupt ( timer_intr ),
      .Freeze ( net_gnd0 )
    );

  opb_uart16550_0_wrapper
    opb_uart16550_0 (
      .OPB_Clk ( opb_clk ),
      .OPB_Rst ( opb_v20_0_OPB_Rst ),
      .IP2INTC_Irpt ( uart_intr ),
      .Freeze ( net_gnd0 ),
      .OPB_ABus ( opb_v20_0_OPB_ABus ),
      .OPB_BE ( opb_v20_0_OPB_BE ),
      .OPB_RNW ( opb_v20_0_OPB_RNW ),
      .OPB_select ( opb_v20_0_OPB_select ),
      .OPB_seqAddr ( opb_v20_0_OPB_seqAddr ),
      .OPB_DBus ( opb_v20_0_OPB_DBus ),
      .Sln_DBus ( opb_v20_0_Sl_DBus[96:127] ),
      .Sln_ErrAck ( opb_v20_0_Sl_errAck[3] ),
      .Sln_Retry ( opb_v20_0_Sl_retry[3] ),
      .Sln_ToutSup ( opb_v20_0_Sl_toutSup[3] ),
      .Sln_XferAck ( opb_v20_0_Sl_xferAck[3] ),
      .baudoutN (  ),
      .ctsN ( net_gnd0 ),
      .dcdN ( net_vcc0 ),
      .ddis (  ),
      .dsrN ( net_vcc0 ),
      .dtrN (  ),
      .out1N (  ),
      .out2N (  ),
      .rclk ( net_gnd0 ),
      .riN ( net_vcc0 ),
      .rtsN (  ),
      .rxrdyN (  ),
      .sin ( uart_RX_IBUF ),
      .sout ( uart_TX_OBUF ),
      .txrdyN (  ),
      .xin ( net_gnd0 ),
      .xout (  )
    );

  opb_gpio_0_wrapper
    opb_gpio_0 (
      .OPB_ABus ( opb_v20_0_OPB_ABus ),
      .OPB_BE ( opb_v20_0_OPB_BE ),
      .OPB_Clk ( opb_clk ),
      .OPB_DBus ( opb_v20_0_OPB_DBus ),
      .OPB_RNW ( opb_v20_0_OPB_RNW ),
      .OPB_Rst ( opb_v20_0_OPB_Rst ),
      .OPB_select ( opb_v20_0_OPB_select ),
      .OPB_seqAddr ( opb_v20_0_OPB_seqAddr ),
      .Sln_DBus ( opb_v20_0_Sl_DBus[128:159] ),
      .Sln_errAck ( opb_v20_0_Sl_errAck[4] ),
      .Sln_retry ( opb_v20_0_Sl_retry[4] ),
      .Sln_toutSup ( opb_v20_0_Sl_toutSup[4] ),
      .Sln_xferAck ( opb_v20_0_Sl_xferAck[4] ),
      .IP2INTC_Irpt (  ),
      .GPIO_in ( net_gnd27 ),
      .GPIO_d_out (  ),
      .GPIO_t_out (  ),
      .GPIO2_in ( gpio2_in ),
      .GPIO2_d_out ( gpio2_d_out[26:0] ),
      .GPIO2_t_out ( gpio2_t_out[26:0] ),
      .GPIO_IO_I ( gpio_I[26:0] ),
      .GPIO_IO_O ( gpio_O[26:0] ),
      .GPIO_IO_T ( gpio_T[26:0] ),
      .GPIO2_IO_I ( net_gnd27 ),
      .GPIO2_IO_O (  ),
      .GPIO2_IO_T (  )
    );

  opb_ps2_dual_ref_0_wrapper
    opb_ps2_dual_ref_0 (
      .OPB_BE ( opb_v20_0_OPB_BE ),
      .IPIF_Rst ( opb_v20_0_OPB_Rst ),
      .OPB_Select ( opb_v20_0_OPB_select ),
      .OPB_DBus ( opb_v20_0_OPB_DBus ),
      .OPB_Clk ( opb_clk ),
      .OPB_ABus ( opb_v20_0_OPB_ABus ),
      .OPB_RNW ( opb_v20_0_OPB_RNW ),
      .OPB_seqAddr ( opb_v20_0_OPB_seqAddr ),
      .Sys_Intr1 ( ps2_1_intr ),
      .Sys_Intr2 ( ps2_2_intr ),
      .Sln_XferAck ( opb_v20_0_Sl_xferAck[5] ),
      .Sln_DBus ( opb_v20_0_Sl_DBus[160:191] ),
      .Sln_DBusEn (  ),
      .Sln_errAck ( opb_v20_0_Sl_errAck[5] ),
      .Sln_retry ( opb_v20_0_Sl_retry[5] ),
      .Sln_toutSup ( opb_v20_0_Sl_toutSup[5] ),
      .Clkin1 ( ps2_clk_rx_1 ),
      .Clkpd1 ( ps2_clk_tx_1 ),
      .Rx1 ( ps2_d_rx_1 ),
      .Txpd1 ( ps2_d_tx_1 ),
      .Clkin2 ( ps2_clk_rx_2 ),
      .Clkpd2 ( ps2_clk_tx_2 ),
      .Rx2 ( ps2_d_rx_2 ),
      .Txpd2 ( ps2_d_tx_2 )
    );

  opb_iic_0_wrapper
    opb_iic_0 (
      .OPB_Clk ( opb_clk ),
      .Sda_I ( iic_sda_int_I ),
      .Sda_O ( iic_sda_int_O ),
      .Sda_T ( iic_sda_int_T ),
      .Scl_I ( iic_scl_int_I ),
      .Scl_O ( iic_scl_int_O ),
      .Scl_T ( iic_scl_int_T ),
      .Gpo (  ),
      .OPB_ABus ( opb_v20_0_OPB_ABus ),
      .OPB_DBus ( opb_v20_0_OPB_DBus ),
      .Sln_DBus ( opb_v20_0_Sl_DBus[192:223] ),
      .OPB_select ( opb_v20_0_OPB_select ),
      .OPB_RNW ( opb_v20_0_OPB_RNW ),
      .Sln_xferAck ( opb_v20_0_Sl_xferAck[6] ),
      .Sln_errAck ( opb_v20_0_Sl_errAck[6] ),
      .Sln_toutSup ( opb_v20_0_Sl_toutSup[6] ),
      .Sln_retry ( opb_v20_0_Sl_retry[6] ),
      .IP2INTC_Irpt ( iic_intr ),
      .OPB_Rst ( opb_v20_0_OPB_Rst ),
      .Freeze ( net_gnd0 ),
      .OPB_seqAddr ( opb_v20_0_OPB_seqAddr ),
      .OPB_BE ( opb_v20_0_OPB_BE )
    );

  opb_ac97_controller_ref_0_wrapper
    opb_ac97_controller_ref_0 (
      .OPB_Clk ( opb_clk ),
      .OPB_Rst ( opb_v20_0_OPB_Rst ),
      .OPB_ABus ( opb_v20_0_OPB_ABus ),
      .OPB_BE ( opb_v20_0_OPB_BE ),
      .OPB_RNW ( opb_v20_0_OPB_RNW ),
      .OPB_select ( opb_v20_0_OPB_select ),
      .OPB_seqAddr ( opb_v20_0_OPB_seqAddr ),
      .OPB_DBus ( opb_v20_0_OPB_DBus ),
      .opb_ac97_controller_DBus ( opb_v20_0_Sl_DBus[224:255] ),
      .opb_ac97_controller_errAck ( opb_v20_0_Sl_errAck[7] ),
      .opb_ac97_controller_retry ( opb_v20_0_Sl_retry[7] ),
      .opb_ac97_controller_toutSup ( opb_v20_0_Sl_toutSup[7] ),
      .opb_ac97_controller_xferAck ( opb_v20_0_Sl_xferAck[7] ),
      .Playback_Interrupt ( ac97_play_intr ),
      .Record_Interrupt ( ac97_record_intr ),
      .Bit_Clk ( ac97_bit_clk_BUFGP ),
      .Sync ( ac97_sync_OBUF ),
      .SData_Out ( ac97_sdata_out_OBUF ),
      .SData_In ( ac97_sdata_in_IBUF )
    );

  plb_v34_0_wrapper
    plb_v34_0 (
      .PLB_Clk ( plb_clk ),
      .SYS_Rst ( sys_rst[0] ),
      .PLB_Rst ( plb_v34_0_PLB_Rst ),
      .PLB_dcrAck ( dcr_v29_0_Sl_dcrAck[0] ),
      .PLB_dcrDBus ( dcr_v29_0_Sl_dcrDBus[0:31] ),
      .DCR_ABus ( dcr_v29_0_DCR_ABus[0:9] ),
      .DCR_DBus ( dcr_v29_0_DCR_Sl_DBus[0:31] ),
      .DCR_Read ( dcr_v29_0_DCR_Read[0] ),
      .DCR_Write ( dcr_v29_0_DCR_Write[0] ),
      .M_ABus ( plb_v34_0_M_ABus ),
      .M_BE ( plb_v34_0_M_BE ),
      .M_RNW ( plb_v34_0_M_RNW ),
      .M_abort ( plb_v34_0_M_abort ),
      .M_busLock ( plb_v34_0_M_busLock ),
      .M_compress ( plb_v34_0_M_compress ),
      .M_guarded ( plb_v34_0_M_guarded ),
      .M_lockErr ( plb_v34_0_M_lockErr ),
      .M_MSize ( plb_v34_0_M_MSize ),
      .M_ordered ( plb_v34_0_M_ordered ),
      .M_priority ( plb_v34_0_M_priority ),
      .M_rdBurst ( plb_v34_0_M_rdBurst ),
      .M_request ( plb_v34_0_M_request ),
      .M_size ( plb_v34_0_M_size ),
      .M_type ( plb_v34_0_M_type ),
      .M_wrBurst ( plb_v34_0_M_wrBurst ),
      .M_wrDBus ( plb_v34_0_M_wrDBus ),
      .Sl_addrAck ( plb_v34_0_Sl_addrAck[0:0] ),
      .Sl_MErr ( plb_v34_0_Sl_MErr ),
      .Sl_MBusy ( plb_v34_0_Sl_MBusy ),
      .Sl_rdBTerm ( plb_v34_0_Sl_rdBTerm[0:0] ),
      .Sl_rdComp ( plb_v34_0_Sl_rdComp[0:0] ),
      .Sl_rdDAck ( plb_v34_0_Sl_rdDAck[0:0] ),
      .Sl_rdDBus ( plb_v34_0_Sl_rdDBus ),
      .Sl_rdWdAddr ( plb_v34_0_Sl_rdWdAddr ),
      .Sl_rearbitrate ( plb_v34_0_Sl_rearbitrate[0:0] ),
      .Sl_SSize ( plb_v34_0_Sl_SSize ),
      .Sl_wait ( plb_v34_0_Sl_wait[0:0] ),
      .Sl_wrBTerm ( plb_v34_0_Sl_wrBTerm[0:0] ),
      .Sl_wrComp ( plb_v34_0_Sl_wrComp[0:0] ),
      .Sl_wrDAck ( plb_v34_0_Sl_wrDAck[0:0] ),
      .PLB_ABus ( plb_v34_0_PLB_ABus ),
      .PLB_BE ( plb_v34_0_PLB_BE ),
      .PLB_MAddrAck ( plb_v34_0_PLB_MAddrAck ),
      .PLB_MBusy ( plb_v34_0_PLB_MBusy ),
      .PLB_MErr ( plb_v34_0_PLB_MErr ),
      .PLB_MRdBTerm ( plb_v34_0_PLB_MRdBTerm ),
      .PLB_MRdDAck ( plb_v34_0_PLB_MRdDAck ),
      .PLB_MRdDBus ( plb_v34_0_PLB_MRdDBus ),
      .PLB_MRdWdAddr ( plb_v34_0_PLB_MRdWdAddr ),
      .PLB_MRearbitrate ( plb_v34_0_PLB_MRearbitrate ),
      .PLB_MWrBTerm ( plb_v34_0_PLB_MWrBTerm ),
      .PLB_MWrDAck ( plb_v34_0_PLB_MWrDAck ),
      .PLB_MSSize ( plb_v34_0_PLB_MSSize ),
      .PLB_PAValid ( plb_v34_0_PLB_PAValid ),
      .PLB_RNW ( plb_v34_0_PLB_RNW ),
      .PLB_SAValid ( plb_v34_0_PLB_SAValid ),
      .PLB_abort ( plb_v34_0_PLB_abort ),
      .PLB_busLock ( plb_v34_0_PLB_busLock ),
      .PLB_compress ( plb_v34_0_PLB_compress ),
      .PLB_guarded ( plb_v34_0_PLB_guarded ),
      .PLB_lockErr ( plb_v34_0_PLB_lockErr ),
      .PLB_masterID ( plb_v34_0_PLB_masterID[0:0] ),
      .PLB_MSize ( plb_v34_0_PLB_MSize ),
      .PLB_ordered ( plb_v34_0_PLB_ordered ),
      .PLB_pendPri ( plb_v34_0_PLB_pendPri ),
      .PLB_pendReq ( plb_v34_0_PLB_pendReq ),
      .PLB_rdBurst ( plb_v34_0_PLB_rdBurst ),
      .PLB_rdPrim ( plb_v34_0_PLB_rdPrim ),
      .PLB_reqPri ( plb_v34_0_PLB_reqPri ),
      .PLB_size ( plb_v34_0_PLB_size ),
      .PLB_type ( plb_v34_0_PLB_type ),
      .PLB_wrBurst ( plb_v34_0_PLB_wrBurst ),
      .PLB_wrDBus ( plb_v34_0_PLB_wrDBus ),
      .PLB_wrPrim ( plb_v34_0_PLB_wrPrim ),
      .PLB_SaddrAck (  ),
      .PLB_SMErr (  ),
      .PLB_SMBusy (  ),
      .PLB_SrdBTerm (  ),
      .PLB_SrdComp (  ),
      .PLB_SrdDAck (  ),
      .PLB_SrdDBus (  ),
      .PLB_SrdWdAddr (  ),
      .PLB_Srearbitrate (  ),
      .PLB_Sssize (  ),
      .PLB_Swait (  ),
      .PLB_SwrBTerm (  ),
      .PLB_SwrComp (  ),
      .PLB_SwrDAck (  ),
      .PLB2OPB_rearb ( net_gnd1[0:0] ),
      .ArbAddrVldReg (  ),
      .Bus_Error_Det ( plb_error_det )
    );

  dcr_v29_0_wrapper
    dcr_v29_0 (
      .M_dcrABus ( dcr_v29_0_M_dcrABus ),
      .M_dcrDBus ( dcr_v29_0_M_dcrDBus ),
      .M_dcrRead ( dcr_v29_0_M_dcrRead ),
      .M_dcrWrite ( dcr_v29_0_M_dcrWrite ),
      .DCR_M_DBus ( dcr_v29_0_DCR_M_DBus ),
      .DCR_Ack ( dcr_v29_0_DCR_Ack ),
      .DCR_ABus ( dcr_v29_0_DCR_ABus ),
      .DCR_Sl_DBus ( dcr_v29_0_DCR_Sl_DBus ),
      .DCR_Read ( dcr_v29_0_DCR_Read ),
      .DCR_Write ( dcr_v29_0_DCR_Write ),
      .Sl_dcrDBus ( dcr_v29_0_Sl_dcrDBus ),
      .Sl_dcrAck ( dcr_v29_0_Sl_dcrAck )
    );

  opb2dcr_bridge_0_wrapper
    opb2dcr_bridge_0 (
      .OPB_Clk ( opb_clk ),
      .OPB_Rst ( opb_v20_0_OPB_Rst ),
      .OPB_dcrClk (  ),
      .OPB_dcrRst (  ),
      .OPB_ABus ( opb_v20_0_OPB_ABus ),
      .OPB_BE ( opb_v20_0_OPB_BE ),
      .OPB_DBus ( opb_v20_0_OPB_DBus ),
      .OPB_RNW ( opb_v20_0_OPB_RNW ),
      .OPB_select ( opb_v20_0_OPB_select ),
      .OPB_seqAddr ( opb_v20_0_OPB_seqAddr ),
      .OPB_xferAck ( opb_v20_0_OPB_xferAck ),
      .OPB_errAck ( opb_v20_0_OPB_errAck ),
      .OPB_retry ( opb_v20_0_OPB_retry ),
      .OPB_timeout ( opb_v20_0_OPB_timeout ),
      .Sln_DBus ( opb_v20_0_Sl_DBus[256:287] ),
      .Sln_ErrAck ( opb_v20_0_Sl_errAck[8] ),
      .Sln_Retry ( opb_v20_0_Sl_retry[8] ),
      .Sln_ToutSup ( opb_v20_0_Sl_toutSup[8] ),
      .Sln_XferAck ( opb_v20_0_Sl_xferAck[8] ),
      .DCR_opbAck ( dcr_v29_0_DCR_Ack ),
      .DCR_opbDBusIn ( dcr_v29_0_DCR_M_DBus ),
      .OPB_dcrRead ( dcr_v29_0_M_dcrRead ),
      .OPB_dcrWrite ( dcr_v29_0_M_dcrWrite ),
      .OPB_dcrABus ( dcr_v29_0_M_dcrABus ),
      .OPB_dcrDBusOut ( dcr_v29_0_M_dcrDBus )
    );

  opb2plb_bridge_0_wrapper
    opb2plb_bridge_0 (
      .OPB_Clk ( opb_clk ),
      .PLB_Clk ( plb_clk ),
      .OPB_Rst ( opb_v20_0_OPB_Rst ),
      .PLB_Rst ( plb_v34_0_PLB_Rst ),
      .BGI_Trans_Abort ( net_gnd0 ),
      .Bus_Error_Det (  ),
      .OPB_select ( opb_v20_0_OPB_select ),
      .OPB_ABus ( opb_v20_0_OPB_ABus ),
      .OPB_RNW ( opb_v20_0_OPB_RNW ),
      .OPB_BE ( opb_v20_0_OPB_BE ),
      .OPB_DBus ( opb_v20_0_OPB_DBus ),
      .OPB_seqAddr ( opb_v20_0_OPB_seqAddr ),
      .BGI_DBus ( opb_v20_0_Sl_DBus[288:319] ),
      .BGI_retry ( opb_v20_0_Sl_retry[9] ),
      .BGI_toutSup ( opb_v20_0_Sl_toutSup[9] ),
      .BGI_xferAck ( opb_v20_0_Sl_xferAck[9] ),
      .BGI_errAck ( opb_v20_0_Sl_errAck[9] ),
      .BGI_request ( plb_v34_0_M_request[0] ),
      .BGI_ABus ( plb_v34_0_M_ABus[0:31] ),
      .BGI_RNW ( plb_v34_0_M_RNW[0] ),
      .BGI_BE ( plb_v34_0_M_BE[0:7] ),
      .BGI_size ( plb_v34_0_M_size[0:3] ),
      .BGI_type ( plb_v34_0_M_type[0:2] ),
      .BGI_priority ( plb_v34_0_M_priority[0:1] ),
      .BGI_rdBurst ( plb_v34_0_M_rdBurst[0] ),
      .BGI_wrBurst ( plb_v34_0_M_wrBurst[0] ),
      .BGI_busLock ( plb_v34_0_M_busLock[0] ),
      .BGI_abort ( plb_v34_0_M_abort[0] ),
      .BGI_lockErr ( plb_v34_0_M_lockErr[0] ),
      .BGI_mSize ( plb_v34_0_M_MSize[0:1] ),
      .BGI_ordered ( plb_v34_0_M_ordered[0] ),
      .BGI_compress ( plb_v34_0_M_compress[0] ),
      .BGI_guarded ( plb_v34_0_M_guarded[0] ),
      .BGI_wrDBus ( plb_v34_0_M_wrDBus[0:63] ),
      .PLB_RdWdAddr ( plb_v34_0_PLB_MRdWdAddr[0:3] ),
      .PLB_RdDBus ( plb_v34_0_PLB_MRdDBus[0:63] ),
      .PLB_AddrAck ( plb_v34_0_PLB_MAddrAck[0] ),
      .PLB_RdDAck ( plb_v34_0_PLB_MRdDAck[0] ),
      .PLB_WrDAck ( plb_v34_0_PLB_MWrDAck[0] ),
      .PLB_rearbitrate ( plb_v34_0_PLB_MRearbitrate[0] ),
      .PLB_Busy ( plb_v34_0_PLB_MBusy[0] ),
      .PLB_Err ( plb_v34_0_PLB_MErr[0] ),
      .PLB_RdBTerm ( plb_v34_0_PLB_MRdBTerm[0] ),
      .PLB_WrBTerm ( plb_v34_0_PLB_MWrBTerm[0] ),
      .PLB_sSize ( plb_v34_0_PLB_MSSize[0:1] ),
      .PLB_pendReq ( net_gnd0 ),
      .PLB_pendPri ( net_gnd2 ),
      .PLB_reqPri ( net_gnd2 ),
      .DCR_Read ( net_gnd0 ),
      .DCR_Write ( net_gnd0 ),
      .DCR_ABus ( net_gnd10 ),
      .DCR_DBus ( net_gnd32 ),
      .BGI_dcr_DBus (  ),
      .BGI_ack (  )
    );

  plb_ddr_0_wrapper
    plb_ddr_0 (
      .PLB_Clk ( plb_clk ),
      .PLB_Clk_n ( plb_clk_n ),
      .Clk90_in ( plb_clk90 ),
      .Clk90_in_n ( plb_clk270 ),
      .DDR_Clk90_in ( ddr_clk_fb90 ),
      .DDR_Clk90_in_n ( ddr_clk_fb270 ),
      .PLB_Rst ( plb_v34_0_PLB_Rst ),
      .PLB_ABus ( plb_v34_0_PLB_ABus ),
      .PLB_PAValid ( plb_v34_0_PLB_PAValid ),
      .PLB_SAValid ( plb_v34_0_PLB_SAValid ),
      .PLB_rdPrim ( plb_v34_0_PLB_rdPrim ),
      .PLB_wrPrim ( plb_v34_0_PLB_wrPrim ),
      .PLB_masterID ( plb_v34_0_PLB_masterID[0:0] ),
      .PLB_abort ( plb_v34_0_PLB_abort ),
      .PLB_busLock ( plb_v34_0_PLB_busLock ),
      .PLB_RNW ( plb_v34_0_PLB_RNW ),
      .PLB_BE ( plb_v34_0_PLB_BE ),
      .PLB_MSize ( plb_v34_0_PLB_MSize ),
      .PLB_size ( plb_v34_0_PLB_size ),
      .PLB_type ( plb_v34_0_PLB_type ),
      .PLB_compress ( plb_v34_0_PLB_compress ),
      .PLB_guarded ( plb_v34_0_PLB_guarded ),
      .PLB_ordered ( plb_v34_0_PLB_ordered ),
      .PLB_lockErr ( plb_v34_0_PLB_lockErr ),
      .PLB_wrDBus ( plb_v34_0_PLB_wrDBus ),
      .PLB_wrBurst ( plb_v34_0_PLB_wrBurst ),
      .PLB_rdBurst ( plb_v34_0_PLB_rdBurst ),
      .PLB_pendReq ( plb_v34_0_PLB_pendReq ),
      .PLB_pendPri ( plb_v34_0_PLB_pendPri ),
      .PLB_reqPri ( plb_v34_0_PLB_reqPri ),
      .Sl_addrAck ( plb_v34_0_Sl_addrAck[0] ),
      .Sl_SSize ( plb_v34_0_Sl_SSize ),
      .Sl_wait ( plb_v34_0_Sl_wait[0] ),
      .Sl_rearbitrate ( plb_v34_0_Sl_rearbitrate[0] ),
      .Sl_wrDAck ( plb_v34_0_Sl_wrDAck[0] ),
      .Sl_wrComp ( plb_v34_0_Sl_wrComp[0] ),
      .Sl_wrBTerm ( plb_v34_0_Sl_wrBTerm[0] ),
      .Sl_rdDBus ( plb_v34_0_Sl_rdDBus ),
      .Sl_rdWdAddr ( plb_v34_0_Sl_rdWdAddr ),
      .Sl_rdDAck ( plb_v34_0_Sl_rdDAck[0] ),
      .Sl_rdComp ( plb_v34_0_Sl_rdComp[0] ),
      .Sl_rdBTerm ( plb_v34_0_Sl_rdBTerm[0] ),
      .Sl_MBusy ( plb_v34_0_Sl_MBusy ),
      .Sl_MErr ( plb_v34_0_Sl_MErr ),
      .IP2INTC_Irpt (  ),
      .DDR_Clk ( ddr_clk_OBUF[0:0] ),
      .DDR_Clkn ( ddr_clkb_OBUF[0:0] ),
      .DDR_CKE ( ddr_cke_OBUF[0:0] ),
      .DDR_CSn ( ddr_csb_OBUF[0:0] ),
      .DDR_RASn ( ddr_rasb_OBUF ),
      .DDR_CASn ( ddr_casb_OBUF ),
      .DDR_WEn ( ddr_web_OBUF ),
      .DDR_DM ( ddr_dm_OBUF[3:0] ),
      .DDR_BankAddr ( ddr_ba_OBUF[1:0] ),
      .DDR_Addr ( ddr_ad_OBUF[12:0] ),
      .DDR_DM_ECC (  ),
      .DDR_Init_done (  ),
      .DDR_DQ_I ( ddr_dq_I[31:0] ),
      .DDR_DQ_O ( ddr_dq_O[31:0] ),
      .DDR_DQ_T ( ddr_dq_T[31:0] ),
      .DDR_DQS_I ( ddr_dqs_I[3:0] ),
      .DDR_DQS_O ( ddr_dqs_O[3:0] ),
      .DDR_DQS_T ( ddr_dqs_T[3:0] ),
      .DDR_DQ_ECC_I ( net_gnd7 ),
      .DDR_DQ_ECC_O (  ),
      .DDR_DQ_ECC_T (  ),
      .DDR_DQS_ECC_I ( net_gnd0 ),
      .DDR_DQS_ECC_O (  ),
      .DDR_DQS_ECC_T (  )
    );

  plb_tft_cntlr_ref_0_wrapper
    plb_tft_cntlr_ref_0 (
      .SYS_plbClk ( plb_clk ),
      .SYS_plbReset ( plb_v34_0_PLB_Rst ),
      .Mn_request ( plb_v34_0_M_request[1] ),
      .Mn_ABus ( plb_v34_0_M_ABus[32:63] ),
      .Mn_RNW ( plb_v34_0_M_RNW[1] ),
      .Mn_BE ( plb_v34_0_M_BE[8:15] ),
      .Mn_size ( plb_v34_0_M_size[4:7] ),
      .Mn_type ( plb_v34_0_M_type[3:5] ),
      .Mn_priority ( plb_v34_0_M_priority[2:3] ),
      .Mn_rdBurst ( plb_v34_0_M_rdBurst[1] ),
      .Mn_wrBurst ( plb_v34_0_M_wrBurst[1] ),
      .Mn_busLock ( plb_v34_0_M_busLock[1] ),
      .Mn_abort ( plb_v34_0_M_abort[1] ),
      .Mn_lockErr ( plb_v34_0_M_lockErr[1] ),
      .Mn_msize ( plb_v34_0_M_MSize[2:3] ),
      .Mn_ordered ( plb_v34_0_M_ordered[1] ),
      .Mn_compress ( plb_v34_0_M_compress[1] ),
      .Mn_guarded ( plb_v34_0_M_guarded[1] ),
      .Mn_wrDBus ( plb_v34_0_M_wrDBus[64:127] ),
      .PLB_MnRdWdAddr ( plb_v34_0_PLB_MRdWdAddr[4:7] ),
      .PLB_MnRdDBus ( plb_v34_0_PLB_MRdDBus[64:127] ),
      .PLB_MnAddrAck ( plb_v34_0_PLB_MAddrAck[1] ),
      .PLB_MnRdDAck ( plb_v34_0_PLB_MRdDAck[1] ),
      .PLB_MnWrDAck ( plb_v34_0_PLB_MWrDAck[1] ),
      .PLB_MnRearbitrate ( plb_v34_0_PLB_MRearbitrate[1] ),
      .PLB_MnBusy ( plb_v34_0_PLB_MBusy[1] ),
      .PLB_MnErr ( plb_v34_0_PLB_MErr[1] ),
      .PLB_MnRdBTerm ( plb_v34_0_PLB_MRdBTerm[1] ),
      .PLB_MnWrBTerm ( plb_v34_0_PLB_MWrBTerm[1] ),
      .PLB_Mnssize ( plb_v34_0_PLB_MSSize[2:3] ),
      .PLB_pendReq ( net_gnd0 ),
      .PLB_pendPri ( net_gnd2 ),
      .PLB_reqPri ( net_gnd2 ),
      .SYS_dcrClk ( dcr_clk ),
      .DCR_Ack ( dcr_v29_0_Sl_dcrAck[1] ),
      .DCR_DBusOut ( dcr_v29_0_Sl_dcrDBus[32:63] ),
      .DCR_ABus ( dcr_v29_0_DCR_ABus[10:19] ),
      .DCR_DBusIn ( dcr_v29_0_DCR_Sl_DBus[32:63] ),
      .DCR_Read ( dcr_v29_0_DCR_Read[1] ),
      .DCR_Write ( dcr_v29_0_DCR_Write[1] ),
      .SYS_tftClk ( tft_clk ),
      .TFT_LCD_HSYNC ( tft_lcd_hsync_OBUF ),
      .TFT_LCD_VSYNC ( tft_lcd_vsync_OBUF ),
      .TFT_LCD_DE (  ),
      .TFT_LCD_CLK ( tft_lcd_clk_OBUF ),
      .TFT_LCD_DPS (  ),
      .TFT_LCD_R ( tft_lcd_r_OBUF ),
      .TFT_LCD_G ( tft_lcd_g_OBUF ),
      .TFT_LCD_B ( tft_lcd_b_OBUF )
    );

  opb_ethernet_0_wrapper
    opb_ethernet_0 (
      .PHY_tx_clk ( phy_tx_clk_BUFGP ),
      .PHY_rx_clk ( phy_rx_clk_BUFGP ),
      .PHY_crs ( phy_crs_IBUF ),
      .PHY_dv ( phy_dv_IBUF ),
      .PHY_rx_data ( phy_rx_data_IBUF ),
      .PHY_col ( phy_col_IBUF ),
      .PHY_rx_er ( phy_rx_er_IBUF ),
      .OPB_ABus ( opb_v20_0_OPB_ABus ),
      .OPB_DBus ( opb_v20_0_OPB_DBus ),
      .OPB_errAck ( net_gnd0 ),
      .OPB_BE ( opb_v20_0_OPB_BE ),
      .OPB_MGrant ( net_gnd0 ),
      .OPB_retry ( net_gnd0 ),
      .OPB_RNW ( opb_v20_0_OPB_RNW ),
      .OPB_select ( opb_v20_0_OPB_select ),
      .OPB_seqAddr ( opb_v20_0_OPB_seqAddr ),
      .OPB_timeout ( net_gnd0 ),
      .OPB_xferAck ( net_gnd0 ),
      .Freeze ( net_gnd0 ),
      .OPB_Clk ( opb_clk ),
      .OPB_Rst ( opb_v20_0_OPB_Rst ),
      .PHY_tx_en ( phy_tx_en_OBUF ),
      .PHY_rx_en (  ),
      .PHY_tx_er ( phy_tx_er_OBUF ),
      .PHY_tx_data ( phy_tx_data_OBUF ),
      .PHY_rst_n ( phy_rst_n_OBUF ),
      .Sln_xferAck ( opb_v20_0_Sl_xferAck[10] ),
      .Sln_errAck ( opb_v20_0_Sl_errAck[10] ),
      .Sln_retry ( opb_v20_0_Sl_retry[10] ),
      .Sln_toutSup ( opb_v20_0_Sl_toutSup[10] ),
      .Sln_DBus ( opb_v20_0_Sl_DBus[320:351] ),
      .Mn_request (  ),
      .Mn_busLock (  ),
      .Mn_select (  ),
      .Mn_RNW (  ),
      .Mn_BE (  ),
      .Mn_seqAddr (  ),
      .Mn_ABus (  ),
      .emac_intrpts (  ),
      .IP2INTC_Irpt (  ),
      .PHY_Mii_clk_I ( phy_mii_clk_I ),
      .PHY_Mii_clk_O ( phy_mii_clk_O ),
      .PHY_Mii_clk_T ( phy_mii_clk_T ),
      .PHY_Mii_data_I ( phy_mii_data_I ),
      .PHY_Mii_data_O ( phy_mii_data_O ),
      .PHY_Mii_data_T ( phy_mii_data_T )
    );

  opb_emc_0_wrapper
    opb_emc_0 (
      .OPB_Clk ( opb_clk ),
      .OPB_Rst ( opb_v20_0_OPB_Rst ),
      .OPB_ABus ( opb_v20_0_OPB_ABus ),
      .OPB_DBus ( opb_v20_0_OPB_DBus ),
      .Sln_DBus ( opb_v20_0_Sl_DBus[352:383] ),
      .OPB_select ( opb_v20_0_OPB_select ),
      .OPB_RNW ( opb_v20_0_OPB_RNW ),
      .OPB_seqAddr ( opb_v20_0_OPB_seqAddr ),
      .OPB_BE ( opb_v20_0_OPB_BE ),
      .Sln_xferAck ( opb_v20_0_Sl_xferAck[11] ),
      .Sln_errAck ( opb_v20_0_Sl_errAck[11] ),
      .Sln_toutSup ( opb_v20_0_Sl_toutSup[11] ),
      .Sln_retry ( opb_v20_0_Sl_retry[11] ),
      .Mem_A ( pgassign2 ),
      .Mem_DQ_I ( sram_flash_data_I[31:0] ),
      .Mem_DQ_O ( sram_flash_data_O[31:0] ),
      .Mem_DQ_T ( sram_flash_data_T[31:0] ),
      .Mem_CEN ( pgassign3 ),
      .Mem_OEN ( pgassign4 ),
      .Mem_WEN ( sram_flash_we_n_OBUF ),
      .Mem_QWEN (  ),
      .Mem_BEN ( sram_bw_OBUF[3:0] ),
      .Mem_RPN (  ),
      .Mem_CE ( pgassign5 ),
      .Mem_ADV_LDN ( sram_adv_ld_n_OBUF ),
      .Mem_LBON ( sram_mode_OBUF ),
      .Mem_CKEN (  ),
      .Mem_RNW (  )
    );

  opb_gpio_exp_hdr_0_wrapper
    opb_gpio_exp_hdr_0 (
      .OPB_ABus ( opb_v20_0_OPB_ABus ),
      .OPB_BE ( opb_v20_0_OPB_BE ),
      .OPB_Clk ( opb_clk ),
      .OPB_DBus ( opb_v20_0_OPB_DBus ),
      .OPB_RNW ( opb_v20_0_OPB_RNW ),
      .OPB_Rst ( opb_v20_0_OPB_Rst ),
      .OPB_select ( opb_v20_0_OPB_select ),
      .OPB_seqAddr ( opb_v20_0_OPB_seqAddr ),
      .Sln_DBus ( opb_v20_0_Sl_DBus[384:415] ),
      .Sln_errAck ( opb_v20_0_Sl_errAck[12] ),
      .Sln_retry ( opb_v20_0_Sl_retry[12] ),
      .Sln_toutSup ( opb_v20_0_Sl_toutSup[12] ),
      .Sln_xferAck ( opb_v20_0_Sl_xferAck[12] ),
      .IP2INTC_Irpt (  ),
      .GPIO_in ( net_gnd32 ),
      .GPIO_d_out (  ),
      .GPIO_t_out (  ),
      .GPIO2_in ( net_gnd32 ),
      .GPIO2_d_out (  ),
      .GPIO2_t_out (  ),
      .GPIO_IO_I ( gpio_exp_hdr1_I[31:0] ),
      .GPIO_IO_O ( gpio_exp_hdr1_O[31:0] ),
      .GPIO_IO_T ( gpio_exp_hdr1_T[31:0] ),
      .GPIO2_IO_I ( gpio_exp_hdr2_I[31:0] ),
      .GPIO2_IO_O ( gpio_exp_hdr2_O[31:0] ),
      .GPIO2_IO_T ( gpio_exp_hdr2_T[31:0] )
    );

  opb_gpio_char_lcd_0_wrapper
    opb_gpio_char_lcd_0 (
      .OPB_ABus ( opb_v20_0_OPB_ABus ),
      .OPB_BE ( opb_v20_0_OPB_BE ),
      .OPB_Clk ( opb_clk ),
      .OPB_DBus ( opb_v20_0_OPB_DBus ),
      .OPB_RNW ( opb_v20_0_OPB_RNW ),
      .OPB_Rst ( opb_v20_0_OPB_Rst ),
      .OPB_select ( opb_v20_0_OPB_select ),
      .OPB_seqAddr ( opb_v20_0_OPB_seqAddr ),
      .Sln_DBus ( opb_v20_0_Sl_DBus[416:447] ),
      .Sln_errAck ( opb_v20_0_Sl_errAck[13] ),
      .Sln_retry ( opb_v20_0_Sl_retry[13] ),
      .Sln_toutSup ( opb_v20_0_Sl_toutSup[13] ),
      .Sln_xferAck ( opb_v20_0_Sl_xferAck[13] ),
      .IP2INTC_Irpt (  ),
      .GPIO_in ( net_gnd7 ),
      .GPIO_d_out (  ),
      .GPIO_t_out (  ),
      .GPIO2_in ( net_gnd7 ),
      .GPIO2_d_out (  ),
      .GPIO2_t_out (  ),
      .GPIO_IO_I ( gpio_char_lcd_I[6:0] ),
      .GPIO_IO_O ( gpio_char_lcd_O[6:0] ),
      .GPIO_IO_T ( gpio_char_lcd_T[6:0] ),
      .GPIO2_IO_I ( net_gnd7 ),
      .GPIO2_IO_O (  ),
      .GPIO2_IO_T (  )
    );

  opb_sysace_0_wrapper
    opb_sysace_0 (
      .OPB_Clk ( opb_clk ),
      .OPB_Rst ( opb_v20_0_OPB_Rst ),
      .OPB_ABus ( opb_v20_0_OPB_ABus ),
      .OPB_DBus ( opb_v20_0_OPB_DBus ),
      .Sln_DBus ( opb_v20_0_Sl_DBus[448:479] ),
      .OPB_select ( opb_v20_0_OPB_select ),
      .OPB_RNW ( opb_v20_0_OPB_RNW ),
      .OPB_seqAddr ( opb_v20_0_OPB_seqAddr ),
      .OPB_BE ( opb_v20_0_OPB_BE ),
      .Sln_xferAck ( opb_v20_0_Sl_xferAck[14] ),
      .Sln_errAck ( opb_v20_0_Sl_errAck[14] ),
      .Sln_toutSup ( opb_v20_0_Sl_toutSup[14] ),
      .Sln_retry ( opb_v20_0_Sl_retry[14] ),
      .SysACE_MPA ( sysace_mpa ),
      .SysACE_CLK ( sysace_clk_in_BUFGP ),
      .SysACE_MPIRQ ( sysace_mpirq_IBUF ),
      .SysACE_MPD_I ( sysace_mpd_i ),
      .SysACE_MPD_O ( sysace_mpd_o ),
      .SysACE_MPD_T ( sysace_mpd_t ),
      .SysACE_CEN ( sace_mpce_OBUF ),
      .SysACE_OEN ( sysace_mpoe ),
      .SysACE_WEN ( sysace_mpwe ),
      .SysACE_IRQ ( sysace_intr )
    );

  opb_emc_usb_0_wrapper
    opb_emc_usb_0 (
      .OPB_Clk ( opb_clk ),
      .OPB_Rst ( opb_v20_0_OPB_Rst ),
      .OPB_ABus ( opb_v20_0_OPB_ABus ),
      .OPB_DBus ( opb_v20_0_OPB_DBus ),
      .Sln_DBus ( opb_v20_0_Sl_DBus[480:511] ),
      .OPB_select ( opb_v20_0_OPB_select ),
      .OPB_RNW ( opb_v20_0_OPB_RNW ),
      .OPB_seqAddr ( opb_v20_0_OPB_seqAddr ),
      .OPB_BE ( opb_v20_0_OPB_BE ),
      .Sln_xferAck ( opb_v20_0_Sl_xferAck[15] ),
      .Sln_errAck ( opb_v20_0_Sl_errAck[15] ),
      .Sln_toutSup ( opb_v20_0_Sl_toutSup[15] ),
      .Sln_retry ( opb_v20_0_Sl_retry[15] ),
      .Mem_A ( usb_addr ),
      .Mem_DQ_I ( usb_data_i ),
      .Mem_DQ_O ( usb_data_o ),
      .Mem_DQ_T ( usb_data_t ),
      .Mem_CEN ( usb_csn_OBUF[0:0] ),
      .Mem_OEN ( usb_rdn[0:0] ),
      .Mem_WEN ( usb_wrn ),
      .Mem_QWEN (  ),
      .Mem_BEN (  ),
      .Mem_RPN (  ),
      .Mem_CE ( usb_ce[0:0] ),
      .Mem_ADV_LDN (  ),
      .Mem_LBON (  ),
      .Mem_CKEN (  ),
      .Mem_RNW (  )
    );

  IBUF
    ibuf_0 (
      .I ( sys_clk_in ),
      .O ( sys_clk_in_IBUF )
    );

  IBUF
    ibuf_1 (
      .I ( sys_rst_in ),
      .O ( sys_rst_in_IBUF )
    );

  IBUF
    ibuf_2 (
      .I ( uart_RX ),
      .O ( uart_RX_IBUF )
    );

  OBUF
    obuf_3 (
      .I ( uart_TX_OBUF ),
      .O ( uart_TX )
    );

  IOBUF
    iobuf_4 (
      .I ( gpio_O[26] ),
      .IO ( gpio[26] ),
      .O ( gpio_I[26] ),
      .T ( gpio_T[26] )
    );

  IOBUF
    iobuf_5 (
      .I ( gpio_O[25] ),
      .IO ( gpio[25] ),
      .O ( gpio_I[25] ),
      .T ( gpio_T[25] )
    );

  IOBUF
    iobuf_6 (
      .I ( gpio_O[24] ),
      .IO ( gpio[24] ),
      .O ( gpio_I[24] ),
      .T ( gpio_T[24] )
    );

  IOBUF
    iobuf_7 (
      .I ( gpio_O[23] ),
      .IO ( gpio[23] ),
      .O ( gpio_I[23] ),
      .T ( gpio_T[23] )
    );

  IOBUF
    iobuf_8 (
      .I ( gpio_O[22] ),
      .IO ( gpio[22] ),
      .O ( gpio_I[22] ),
      .T ( gpio_T[22] )
    );

  IOBUF
    iobuf_9 (
      .I ( gpio_O[21] ),
      .IO ( gpio[21] ),
      .O ( gpio_I[21] ),
      .T ( gpio_T[21] )
    );

  IOBUF
    iobuf_10 (
      .I ( gpio_O[20] ),
      .IO ( gpio[20] ),
      .O ( gpio_I[20] ),
      .T ( gpio_T[20] )
    );

  IOBUF
    iobuf_11 (
      .I ( gpio_O[19] ),
      .IO ( gpio[19] ),
      .O ( gpio_I[19] ),
      .T ( gpio_T[19] )
    );

  IOBUF
    iobuf_12 (
      .I ( gpio_O[18] ),
      .IO ( gpio[18] ),
      .O ( gpio_I[18] ),
      .T ( gpio_T[18] )
    );

  IOBUF
    iobuf_13 (
      .I ( gpio_O[17] ),
      .IO ( gpio[17] ),
      .O ( gpio_I[17] ),
      .T ( gpio_T[17] )
    );

  IOBUF
    iobuf_14 (
      .I ( gpio_O[16] ),
      .IO ( gpio[16] ),
      .O ( gpio_I[16] ),
      .T ( gpio_T[16] )
    );

  IOBUF
    iobuf_15 (
      .I ( gpio_O[15] ),
      .IO ( gpio[15] ),
      .O ( gpio_I[15] ),
      .T ( gpio_T[15] )
    );

  IOBUF
    iobuf_16 (
      .I ( gpio_O[14] ),
      .IO ( gpio[14] ),
      .O ( gpio_I[14] ),
      .T ( gpio_T[14] )
    );

  IOBUF
    iobuf_17 (
      .I ( gpio_O[13] ),
      .IO ( gpio[13] ),
      .O ( gpio_I[13] ),
      .T ( gpio_T[13] )
    );

  IOBUF
    iobuf_18 (
      .I ( gpio_O[12] ),
      .IO ( gpio[12] ),
      .O ( gpio_I[12] ),
      .T ( gpio_T[12] )
    );

  IOBUF
    iobuf_19 (
      .I ( gpio_O[11] ),
      .IO ( gpio[11] ),
      .O ( gpio_I[11] ),
      .T ( gpio_T[11] )
    );

  IOBUF
    iobuf_20 (
      .I ( gpio_O[10] ),
      .IO ( gpio[10] ),
      .O ( gpio_I[10] ),
      .T ( gpio_T[10] )
    );

  IOBUF
    iobuf_21 (
      .I ( gpio_O[9] ),
      .IO ( gpio[9] ),
      .O ( gpio_I[9] ),
      .T ( gpio_T[9] )
    );

  IOBUF
    iobuf_22 (
      .I ( gpio_O[8] ),
      .IO ( gpio[8] ),
      .O ( gpio_I[8] ),
      .T ( gpio_T[8] )
    );

  IOBUF
    iobuf_23 (
      .I ( gpio_O[7] ),
      .IO ( gpio[7] ),
      .O ( gpio_I[7] ),
      .T ( gpio_T[7] )
    );

  IOBUF
    iobuf_24 (
      .I ( gpio_O[6] ),
      .IO ( gpio[6] ),
      .O ( gpio_I[6] ),
      .T ( gpio_T[6] )
    );

  IOBUF
    iobuf_25 (
      .I ( gpio_O[5] ),
      .IO ( gpio[5] ),
      .O ( gpio_I[5] ),
      .T ( gpio_T[5] )
    );

  IOBUF
    iobuf_26 (
      .I ( gpio_O[4] ),
      .IO ( gpio[4] ),
      .O ( gpio_I[4] ),
      .T ( gpio_T[4] )
    );

  IOBUF
    iobuf_27 (
      .I ( gpio_O[3] ),
      .IO ( gpio[3] ),
      .O ( gpio_I[3] ),
      .T ( gpio_T[3] )
    );

  IOBUF
    iobuf_28 (
      .I ( gpio_O[2] ),
      .IO ( gpio[2] ),
      .O ( gpio_I[2] ),
      .T ( gpio_T[2] )
    );

  IOBUF
    iobuf_29 (
      .I ( gpio_O[1] ),
      .IO ( gpio[1] ),
      .O ( gpio_I[1] ),
      .T ( gpio_T[1] )
    );

  IOBUF
    iobuf_30 (
      .I ( gpio_O[0] ),
      .IO ( gpio[0] ),
      .O ( gpio_I[0] ),
      .T ( gpio_T[0] )
    );

  IOBUF
    iobuf_31 (
      .I ( gpio_exp_hdr1_O[31] ),
      .IO ( gpio_exp_hdr1[31] ),
      .O ( gpio_exp_hdr1_I[31] ),
      .T ( gpio_exp_hdr1_T[31] )
    );

  IOBUF
    iobuf_32 (
      .I ( gpio_exp_hdr1_O[30] ),
      .IO ( gpio_exp_hdr1[30] ),
      .O ( gpio_exp_hdr1_I[30] ),
      .T ( gpio_exp_hdr1_T[30] )
    );

  IOBUF
    iobuf_33 (
      .I ( gpio_exp_hdr1_O[29] ),
      .IO ( gpio_exp_hdr1[29] ),
      .O ( gpio_exp_hdr1_I[29] ),
      .T ( gpio_exp_hdr1_T[29] )
    );

  IOBUF
    iobuf_34 (
      .I ( gpio_exp_hdr1_O[28] ),
      .IO ( gpio_exp_hdr1[28] ),
      .O ( gpio_exp_hdr1_I[28] ),
      .T ( gpio_exp_hdr1_T[28] )
    );

  IOBUF
    iobuf_35 (
      .I ( gpio_exp_hdr1_O[27] ),
      .IO ( gpio_exp_hdr1[27] ),
      .O ( gpio_exp_hdr1_I[27] ),
      .T ( gpio_exp_hdr1_T[27] )
    );

  IOBUF
    iobuf_36 (
      .I ( gpio_exp_hdr1_O[26] ),
      .IO ( gpio_exp_hdr1[26] ),
      .O ( gpio_exp_hdr1_I[26] ),
      .T ( gpio_exp_hdr1_T[26] )
    );

  IOBUF
    iobuf_37 (
      .I ( gpio_exp_hdr1_O[25] ),
      .IO ( gpio_exp_hdr1[25] ),
      .O ( gpio_exp_hdr1_I[25] ),
      .T ( gpio_exp_hdr1_T[25] )
    );

  IOBUF
    iobuf_38 (
      .I ( gpio_exp_hdr1_O[24] ),
      .IO ( gpio_exp_hdr1[24] ),
      .O ( gpio_exp_hdr1_I[24] ),
      .T ( gpio_exp_hdr1_T[24] )
    );

  IOBUF
    iobuf_39 (
      .I ( gpio_exp_hdr1_O[23] ),
      .IO ( gpio_exp_hdr1[23] ),
      .O ( gpio_exp_hdr1_I[23] ),
      .T ( gpio_exp_hdr1_T[23] )
    );

  IOBUF
    iobuf_40 (
      .I ( gpio_exp_hdr1_O[22] ),
      .IO ( gpio_exp_hdr1[22] ),
      .O ( gpio_exp_hdr1_I[22] ),
      .T ( gpio_exp_hdr1_T[22] )
    );

  IOBUF
    iobuf_41 (
      .I ( gpio_exp_hdr1_O[21] ),
      .IO ( gpio_exp_hdr1[21] ),
      .O ( gpio_exp_hdr1_I[21] ),
      .T ( gpio_exp_hdr1_T[21] )
    );

  IOBUF
    iobuf_42 (
      .I ( gpio_exp_hdr1_O[20] ),
      .IO ( gpio_exp_hdr1[20] ),
      .O ( gpio_exp_hdr1_I[20] ),
      .T ( gpio_exp_hdr1_T[20] )
    );

  IOBUF
    iobuf_43 (
      .I ( gpio_exp_hdr1_O[19] ),
      .IO ( gpio_exp_hdr1[19] ),
      .O ( gpio_exp_hdr1_I[19] ),
      .T ( gpio_exp_hdr1_T[19] )
    );

  IOBUF
    iobuf_44 (
      .I ( gpio_exp_hdr1_O[18] ),
      .IO ( gpio_exp_hdr1[18] ),
      .O ( gpio_exp_hdr1_I[18] ),
      .T ( gpio_exp_hdr1_T[18] )
    );

  IOBUF
    iobuf_45 (
      .I ( gpio_exp_hdr1_O[17] ),
      .IO ( gpio_exp_hdr1[17] ),
      .O ( gpio_exp_hdr1_I[17] ),
      .T ( gpio_exp_hdr1_T[17] )
    );

  IOBUF
    iobuf_46 (
      .I ( gpio_exp_hdr1_O[16] ),
      .IO ( gpio_exp_hdr1[16] ),
      .O ( gpio_exp_hdr1_I[16] ),
      .T ( gpio_exp_hdr1_T[16] )
    );

  IOBUF
    iobuf_47 (
      .I ( gpio_exp_hdr1_O[15] ),
      .IO ( gpio_exp_hdr1[15] ),
      .O ( gpio_exp_hdr1_I[15] ),
      .T ( gpio_exp_hdr1_T[15] )
    );

  IOBUF
    iobuf_48 (
      .I ( gpio_exp_hdr1_O[14] ),
      .IO ( gpio_exp_hdr1[14] ),
      .O ( gpio_exp_hdr1_I[14] ),
      .T ( gpio_exp_hdr1_T[14] )
    );

  IOBUF
    iobuf_49 (
      .I ( gpio_exp_hdr1_O[13] ),
      .IO ( gpio_exp_hdr1[13] ),
      .O ( gpio_exp_hdr1_I[13] ),
      .T ( gpio_exp_hdr1_T[13] )
    );

  IOBUF
    iobuf_50 (
      .I ( gpio_exp_hdr1_O[12] ),
      .IO ( gpio_exp_hdr1[12] ),
      .O ( gpio_exp_hdr1_I[12] ),
      .T ( gpio_exp_hdr1_T[12] )
    );

  IOBUF
    iobuf_51 (
      .I ( gpio_exp_hdr1_O[11] ),
      .IO ( gpio_exp_hdr1[11] ),
      .O ( gpio_exp_hdr1_I[11] ),
      .T ( gpio_exp_hdr1_T[11] )
    );

  IOBUF
    iobuf_52 (
      .I ( gpio_exp_hdr1_O[10] ),
      .IO ( gpio_exp_hdr1[10] ),
      .O ( gpio_exp_hdr1_I[10] ),
      .T ( gpio_exp_hdr1_T[10] )
    );

  IOBUF
    iobuf_53 (
      .I ( gpio_exp_hdr1_O[9] ),
      .IO ( gpio_exp_hdr1[9] ),
      .O ( gpio_exp_hdr1_I[9] ),
      .T ( gpio_exp_hdr1_T[9] )
    );

  IOBUF
    iobuf_54 (
      .I ( gpio_exp_hdr1_O[8] ),
      .IO ( gpio_exp_hdr1[8] ),
      .O ( gpio_exp_hdr1_I[8] ),
      .T ( gpio_exp_hdr1_T[8] )
    );

  IOBUF
    iobuf_55 (
      .I ( gpio_exp_hdr1_O[7] ),
      .IO ( gpio_exp_hdr1[7] ),
      .O ( gpio_exp_hdr1_I[7] ),
      .T ( gpio_exp_hdr1_T[7] )
    );

  IOBUF
    iobuf_56 (
      .I ( gpio_exp_hdr1_O[6] ),
      .IO ( gpio_exp_hdr1[6] ),
      .O ( gpio_exp_hdr1_I[6] ),
      .T ( gpio_exp_hdr1_T[6] )
    );

  IOBUF
    iobuf_57 (
      .I ( gpio_exp_hdr1_O[5] ),
      .IO ( gpio_exp_hdr1[5] ),
      .O ( gpio_exp_hdr1_I[5] ),
      .T ( gpio_exp_hdr1_T[5] )
    );

  IOBUF
    iobuf_58 (
      .I ( gpio_exp_hdr1_O[4] ),
      .IO ( gpio_exp_hdr1[4] ),
      .O ( gpio_exp_hdr1_I[4] ),
      .T ( gpio_exp_hdr1_T[4] )
    );

  IOBUF
    iobuf_59 (
      .I ( gpio_exp_hdr1_O[3] ),
      .IO ( gpio_exp_hdr1[3] ),
      .O ( gpio_exp_hdr1_I[3] ),
      .T ( gpio_exp_hdr1_T[3] )
    );

  IOBUF
    iobuf_60 (
      .I ( gpio_exp_hdr1_O[2] ),
      .IO ( gpio_exp_hdr1[2] ),
      .O ( gpio_exp_hdr1_I[2] ),
      .T ( gpio_exp_hdr1_T[2] )
    );

  IOBUF
    iobuf_61 (
      .I ( gpio_exp_hdr1_O[1] ),
      .IO ( gpio_exp_hdr1[1] ),
      .O ( gpio_exp_hdr1_I[1] ),
      .T ( gpio_exp_hdr1_T[1] )
    );

  IOBUF
    iobuf_62 (
      .I ( gpio_exp_hdr1_O[0] ),
      .IO ( gpio_exp_hdr1[0] ),
      .O ( gpio_exp_hdr1_I[0] ),
      .T ( gpio_exp_hdr1_T[0] )
    );

  IOBUF
    iobuf_63 (
      .I ( gpio_exp_hdr2_O[31] ),
      .IO ( gpio_exp_hdr2[31] ),
      .O ( gpio_exp_hdr2_I[31] ),
      .T ( gpio_exp_hdr2_T[31] )
    );

  IOBUF
    iobuf_64 (
      .I ( gpio_exp_hdr2_O[30] ),
      .IO ( gpio_exp_hdr2[30] ),
      .O ( gpio_exp_hdr2_I[30] ),
      .T ( gpio_exp_hdr2_T[30] )
    );

  IOBUF
    iobuf_65 (
      .I ( gpio_exp_hdr2_O[29] ),
      .IO ( gpio_exp_hdr2[29] ),
      .O ( gpio_exp_hdr2_I[29] ),
      .T ( gpio_exp_hdr2_T[29] )
    );

  IOBUF
    iobuf_66 (
      .I ( gpio_exp_hdr2_O[28] ),
      .IO ( gpio_exp_hdr2[28] ),
      .O ( gpio_exp_hdr2_I[28] ),
      .T ( gpio_exp_hdr2_T[28] )
    );

  IOBUF
    iobuf_67 (
      .I ( gpio_exp_hdr2_O[27] ),
      .IO ( gpio_exp_hdr2[27] ),
      .O ( gpio_exp_hdr2_I[27] ),
      .T ( gpio_exp_hdr2_T[27] )
    );

  IOBUF
    iobuf_68 (
      .I ( gpio_exp_hdr2_O[26] ),
      .IO ( gpio_exp_hdr2[26] ),
      .O ( gpio_exp_hdr2_I[26] ),
      .T ( gpio_exp_hdr2_T[26] )
    );

  IOBUF
    iobuf_69 (
      .I ( gpio_exp_hdr2_O[25] ),
      .IO ( gpio_exp_hdr2[25] ),
      .O ( gpio_exp_hdr2_I[25] ),
      .T ( gpio_exp_hdr2_T[25] )
    );

  IOBUF
    iobuf_70 (
      .I ( gpio_exp_hdr2_O[24] ),
      .IO ( gpio_exp_hdr2[24] ),
      .O ( gpio_exp_hdr2_I[24] ),
      .T ( gpio_exp_hdr2_T[24] )
    );

  IOBUF
    iobuf_71 (
      .I ( gpio_exp_hdr2_O[23] ),
      .IO ( gpio_exp_hdr2[23] ),
      .O ( gpio_exp_hdr2_I[23] ),
      .T ( gpio_exp_hdr2_T[23] )
    );

  IOBUF
    iobuf_72 (
      .I ( gpio_exp_hdr2_O[22] ),
      .IO ( gpio_exp_hdr2[22] ),
      .O ( gpio_exp_hdr2_I[22] ),
      .T ( gpio_exp_hdr2_T[22] )
    );

  IOBUF
    iobuf_73 (
      .I ( gpio_exp_hdr2_O[21] ),
      .IO ( gpio_exp_hdr2[21] ),
      .O ( gpio_exp_hdr2_I[21] ),
      .T ( gpio_exp_hdr2_T[21] )
    );

  IOBUF
    iobuf_74 (
      .I ( gpio_exp_hdr2_O[20] ),
      .IO ( gpio_exp_hdr2[20] ),
      .O ( gpio_exp_hdr2_I[20] ),
      .T ( gpio_exp_hdr2_T[20] )
    );

  IOBUF
    iobuf_75 (
      .I ( gpio_exp_hdr2_O[19] ),
      .IO ( gpio_exp_hdr2[19] ),
      .O ( gpio_exp_hdr2_I[19] ),
      .T ( gpio_exp_hdr2_T[19] )
    );

  IOBUF
    iobuf_76 (
      .I ( gpio_exp_hdr2_O[18] ),
      .IO ( gpio_exp_hdr2[18] ),
      .O ( gpio_exp_hdr2_I[18] ),
      .T ( gpio_exp_hdr2_T[18] )
    );

  IOBUF
    iobuf_77 (
      .I ( gpio_exp_hdr2_O[17] ),
      .IO ( gpio_exp_hdr2[17] ),
      .O ( gpio_exp_hdr2_I[17] ),
      .T ( gpio_exp_hdr2_T[17] )
    );

  IOBUF
    iobuf_78 (
      .I ( gpio_exp_hdr2_O[16] ),
      .IO ( gpio_exp_hdr2[16] ),
      .O ( gpio_exp_hdr2_I[16] ),
      .T ( gpio_exp_hdr2_T[16] )
    );

  IOBUF
    iobuf_79 (
      .I ( gpio_exp_hdr2_O[15] ),
      .IO ( gpio_exp_hdr2[15] ),
      .O ( gpio_exp_hdr2_I[15] ),
      .T ( gpio_exp_hdr2_T[15] )
    );

  IOBUF
    iobuf_80 (
      .I ( gpio_exp_hdr2_O[14] ),
      .IO ( gpio_exp_hdr2[14] ),
      .O ( gpio_exp_hdr2_I[14] ),
      .T ( gpio_exp_hdr2_T[14] )
    );

  IOBUF
    iobuf_81 (
      .I ( gpio_exp_hdr2_O[13] ),
      .IO ( gpio_exp_hdr2[13] ),
      .O ( gpio_exp_hdr2_I[13] ),
      .T ( gpio_exp_hdr2_T[13] )
    );

  IOBUF
    iobuf_82 (
      .I ( gpio_exp_hdr2_O[12] ),
      .IO ( gpio_exp_hdr2[12] ),
      .O ( gpio_exp_hdr2_I[12] ),
      .T ( gpio_exp_hdr2_T[12] )
    );

  IOBUF
    iobuf_83 (
      .I ( gpio_exp_hdr2_O[11] ),
      .IO ( gpio_exp_hdr2[11] ),
      .O ( gpio_exp_hdr2_I[11] ),
      .T ( gpio_exp_hdr2_T[11] )
    );

  IOBUF
    iobuf_84 (
      .I ( gpio_exp_hdr2_O[10] ),
      .IO ( gpio_exp_hdr2[10] ),
      .O ( gpio_exp_hdr2_I[10] ),
      .T ( gpio_exp_hdr2_T[10] )
    );

  IOBUF
    iobuf_85 (
      .I ( gpio_exp_hdr2_O[9] ),
      .IO ( gpio_exp_hdr2[9] ),
      .O ( gpio_exp_hdr2_I[9] ),
      .T ( gpio_exp_hdr2_T[9] )
    );

  IOBUF
    iobuf_86 (
      .I ( gpio_exp_hdr2_O[8] ),
      .IO ( gpio_exp_hdr2[8] ),
      .O ( gpio_exp_hdr2_I[8] ),
      .T ( gpio_exp_hdr2_T[8] )
    );

  IOBUF
    iobuf_87 (
      .I ( gpio_exp_hdr2_O[7] ),
      .IO ( gpio_exp_hdr2[7] ),
      .O ( gpio_exp_hdr2_I[7] ),
      .T ( gpio_exp_hdr2_T[7] )
    );

  IOBUF
    iobuf_88 (
      .I ( gpio_exp_hdr2_O[6] ),
      .IO ( gpio_exp_hdr2[6] ),
      .O ( gpio_exp_hdr2_I[6] ),
      .T ( gpio_exp_hdr2_T[6] )
    );

  IOBUF
    iobuf_89 (
      .I ( gpio_exp_hdr2_O[5] ),
      .IO ( gpio_exp_hdr2[5] ),
      .O ( gpio_exp_hdr2_I[5] ),
      .T ( gpio_exp_hdr2_T[5] )
    );

  IOBUF
    iobuf_90 (
      .I ( gpio_exp_hdr2_O[4] ),
      .IO ( gpio_exp_hdr2[4] ),
      .O ( gpio_exp_hdr2_I[4] ),
      .T ( gpio_exp_hdr2_T[4] )
    );

  IOBUF
    iobuf_91 (
      .I ( gpio_exp_hdr2_O[3] ),
      .IO ( gpio_exp_hdr2[3] ),
      .O ( gpio_exp_hdr2_I[3] ),
      .T ( gpio_exp_hdr2_T[3] )
    );

  IOBUF
    iobuf_92 (
      .I ( gpio_exp_hdr2_O[2] ),
      .IO ( gpio_exp_hdr2[2] ),
      .O ( gpio_exp_hdr2_I[2] ),
      .T ( gpio_exp_hdr2_T[2] )
    );

  IOBUF
    iobuf_93 (
      .I ( gpio_exp_hdr2_O[1] ),
      .IO ( gpio_exp_hdr2[1] ),
      .O ( gpio_exp_hdr2_I[1] ),
      .T ( gpio_exp_hdr2_T[1] )
    );

  IOBUF
    iobuf_94 (
      .I ( gpio_exp_hdr2_O[0] ),
      .IO ( gpio_exp_hdr2[0] ),
      .O ( gpio_exp_hdr2_I[0] ),
      .T ( gpio_exp_hdr2_T[0] )
    );

  IOBUF
    iobuf_95 (
      .I ( gpio_char_lcd_O[6] ),
      .IO ( gpio_char_lcd[6] ),
      .O ( gpio_char_lcd_I[6] ),
      .T ( gpio_char_lcd_T[6] )
    );

  IOBUF
    iobuf_96 (
      .I ( gpio_char_lcd_O[5] ),
      .IO ( gpio_char_lcd[5] ),
      .O ( gpio_char_lcd_I[5] ),
      .T ( gpio_char_lcd_T[5] )
    );

  IOBUF
    iobuf_97 (
      .I ( gpio_char_lcd_O[4] ),
      .IO ( gpio_char_lcd[4] ),
      .O ( gpio_char_lcd_I[4] ),
      .T ( gpio_char_lcd_T[4] )
    );

  IOBUF
    iobuf_98 (
      .I ( gpio_char_lcd_O[3] ),
      .IO ( gpio_char_lcd[3] ),
      .O ( gpio_char_lcd_I[3] ),
      .T ( gpio_char_lcd_T[3] )
    );

  IOBUF
    iobuf_99 (
      .I ( gpio_char_lcd_O[2] ),
      .IO ( gpio_char_lcd[2] ),
      .O ( gpio_char_lcd_I[2] ),
      .T ( gpio_char_lcd_T[2] )
    );

  IOBUF
    iobuf_100 (
      .I ( gpio_char_lcd_O[1] ),
      .IO ( gpio_char_lcd[1] ),
      .O ( gpio_char_lcd_I[1] ),
      .T ( gpio_char_lcd_T[1] )
    );

  IOBUF
    iobuf_101 (
      .I ( gpio_char_lcd_O[0] ),
      .IO ( gpio_char_lcd[0] ),
      .O ( gpio_char_lcd_I[0] ),
      .T ( gpio_char_lcd_T[0] )
    );

  IOBUF
    iobuf_102 (
      .I ( ps2_mouse_clk_O ),
      .IO ( ps2_mouse_clk ),
      .O ( ps2_mouse_clk_I ),
      .T ( ps2_mouse_clk_T )
    );

  IOBUF
    iobuf_103 (
      .I ( ps2_mouse_data_O ),
      .IO ( ps2_mouse_data ),
      .O ( ps2_mouse_data_I ),
      .T ( ps2_mouse_data_T )
    );

  IOBUF
    iobuf_104 (
      .I ( ps2_keyb_clk_O ),
      .IO ( ps2_keyb_clk ),
      .O ( ps2_keyb_clk_I ),
      .T ( ps2_keyb_clk_T )
    );

  IOBUF
    iobuf_105 (
      .I ( ps2_keyb_data_O ),
      .IO ( ps2_keyb_data ),
      .O ( ps2_keyb_data_I ),
      .T ( ps2_keyb_data_T )
    );

  IOBUF
    iobuf_106 (
      .I ( iic_scl_O ),
      .IO ( iic_scl ),
      .O ( iic_scl_I ),
      .T ( iic_scl_T )
    );

  IOBUF
    iobuf_107 (
      .I ( iic_sda_O ),
      .IO ( iic_sda ),
      .O ( iic_sda_I ),
      .T ( iic_sda_T )
    );

  OBUF
    obuf_108 (
      .I ( sys_rst_n ),
      .O ( ac97_reset_n )
    );

  IBUF
    ibuf_109 (
      .I ( ac97_sdata_In ),
      .O ( ac97_sdata_in_IBUF )
    );

  OBUF
    obuf_110 (
      .I ( ac97_sdata_out_OBUF ),
      .O ( ac97_sdata_Out )
    );

  OBUF
    obuf_111 (
      .I ( ac97_sync_OBUF ),
      .O ( ac97_sync )
    );

  BUFGP
    bufgp_112 (
      .I ( ac97_bit_clk ),
      .O ( ac97_bit_clk_BUFGP )
    );

  OBUF
    obuf_113 (
      .I ( phy_rst_n_OBUF ),
      .O ( phy_rst_n )
    );

  IBUF
    ibuf_114 (
      .I ( phy_mii_int_n ),
      .O ( phy_mii_int_n_IBUF )
    );

  IBUF
    ibuf_115 (
      .I ( phy_col ),
      .O ( phy_col_IBUF )
    );

  IBUF
    ibuf_116 (
      .I ( phy_crs ),
      .O ( phy_crs_IBUF )
    );

  IBUF
    ibuf_117 (
      .I ( phy_dv ),
      .O ( phy_dv_IBUF )
    );

  IOBUF
    iobuf_118 (
      .I ( phy_mii_clk_O ),
      .IO ( phy_mii_clk ),
      .O ( phy_mii_clk_I ),
      .T ( phy_mii_clk_T )
    );

  IOBUF
    iobuf_119 (
      .I ( phy_mii_data_O ),
      .IO ( phy_mii_data ),
      .O ( phy_mii_data_I ),
      .T ( phy_mii_data_T )
    );

  BUFGP
    bufgp_120 (
      .I ( phy_rx_clk ),
      .O ( phy_rx_clk_BUFGP )
    );

  IBUF
    ibuf_121 (
      .I ( phy_rx_data[3] ),
      .O ( phy_rx_data_IBUF[3] )
    );

  IBUF
    ibuf_122 (
      .I ( phy_rx_data[2] ),
      .O ( phy_rx_data_IBUF[2] )
    );

  IBUF
    ibuf_123 (
      .I ( phy_rx_data[1] ),
      .O ( phy_rx_data_IBUF[1] )
    );

  IBUF
    ibuf_124 (
      .I ( phy_rx_data[0] ),
      .O ( phy_rx_data_IBUF[0] )
    );

  IBUF
    ibuf_125 (
      .I ( phy_rx_er ),
      .O ( phy_rx_er_IBUF )
    );

  BUFGP
    bufgp_126 (
      .I ( phy_tx_clk ),
      .O ( phy_tx_clk_BUFGP )
    );

  OBUF
    obuf_127 (
      .I ( phy_tx_data_OBUF[3] ),
      .O ( phy_tx_data[3] )
    );

  OBUF
    obuf_128 (
      .I ( phy_tx_data_OBUF[2] ),
      .O ( phy_tx_data[2] )
    );

  OBUF
    obuf_129 (
      .I ( phy_tx_data_OBUF[1] ),
      .O ( phy_tx_data[1] )
    );

  OBUF
    obuf_130 (
      .I ( phy_tx_data_OBUF[0] ),
      .O ( phy_tx_data[0] )
    );

  OBUF
    obuf_131 (
      .I ( phy_tx_en_OBUF ),
      .O ( phy_tx_en )
    );

  OBUF
    obuf_132 (
      .I ( phy_tx_er_OBUF ),
      .O ( phy_tx_er )
    );

  IBUF
    ibuf_133 (
      .I ( ddr_clk_fb ),
      .O ( ddr_clk_fb_IBUF )
    );

  OBUF
    obuf_134 (
      .I ( ddr_ad_OBUF[12] ),
      .O ( ddr_ad[12] )
    );

  OBUF
    obuf_135 (
      .I ( ddr_ad_OBUF[11] ),
      .O ( ddr_ad[11] )
    );

  OBUF
    obuf_136 (
      .I ( ddr_ad_OBUF[10] ),
      .O ( ddr_ad[10] )
    );

  OBUF
    obuf_137 (
      .I ( ddr_ad_OBUF[9] ),
      .O ( ddr_ad[9] )
    );

  OBUF
    obuf_138 (
      .I ( ddr_ad_OBUF[8] ),
      .O ( ddr_ad[8] )
    );

  OBUF
    obuf_139 (
      .I ( ddr_ad_OBUF[7] ),
      .O ( ddr_ad[7] )
    );

  OBUF
    obuf_140 (
      .I ( ddr_ad_OBUF[6] ),
      .O ( ddr_ad[6] )
    );

  OBUF
    obuf_141 (
      .I ( ddr_ad_OBUF[5] ),
      .O ( ddr_ad[5] )
    );

  OBUF
    obuf_142 (
      .I ( ddr_ad_OBUF[4] ),
      .O ( ddr_ad[4] )
    );

  OBUF
    obuf_143 (
      .I ( ddr_ad_OBUF[3] ),
      .O ( ddr_ad[3] )
    );

  OBUF
    obuf_144 (
      .I ( ddr_ad_OBUF[2] ),
      .O ( ddr_ad[2] )
    );

  OBUF
    obuf_145 (
      .I ( ddr_ad_OBUF[1] ),
      .O ( ddr_ad[1] )
    );

  OBUF
    obuf_146 (
      .I ( ddr_ad_OBUF[0] ),
      .O ( ddr_ad[0] )
    );

  OBUF
    obuf_147 (
      .I ( ddr_ba_OBUF[1] ),
      .O ( ddr_ba[1] )
    );

  OBUF
    obuf_148 (
      .I ( ddr_ba_OBUF[0] ),
      .O ( ddr_ba[0] )
    );

  OBUF
    obuf_149 (
      .I ( ddr_casb_OBUF ),
      .O ( ddr_casb )
    );

  OBUF
    obuf_150 (
      .I ( ddr_cke_OBUF[0] ),
      .O ( ddr_cke )
    );

  OBUF
    obuf_151 (
      .I ( ddr_clk_OBUF[0] ),
      .O ( ddr_clk )
    );

  OBUF
    obuf_152 (
      .I ( ddr_clkb_OBUF[0] ),
      .O ( ddr_clkb )
    );

  OBUF
    obuf_153 (
      .I ( ddr_csb_OBUF[0] ),
      .O ( ddr_csb )
    );

  OBUF
    obuf_154 (
      .I ( ddr_dm_OBUF[3] ),
      .O ( ddr_dm[3] )
    );

  OBUF
    obuf_155 (
      .I ( ddr_dm_OBUF[2] ),
      .O ( ddr_dm[2] )
    );

  OBUF
    obuf_156 (
      .I ( ddr_dm_OBUF[1] ),
      .O ( ddr_dm[1] )
    );

  OBUF
    obuf_157 (
      .I ( ddr_dm_OBUF[0] ),
      .O ( ddr_dm[0] )
    );

  IOBUF
    iobuf_158 (
      .I ( ddr_dq_O[31] ),
      .IO ( ddr_dq[31] ),
      .O ( ddr_dq_I[31] ),
      .T ( ddr_dq_T[31] )
    );

  IOBUF
    iobuf_159 (
      .I ( ddr_dq_O[30] ),
      .IO ( ddr_dq[30] ),
      .O ( ddr_dq_I[30] ),
      .T ( ddr_dq_T[30] )
    );

  IOBUF
    iobuf_160 (
      .I ( ddr_dq_O[29] ),
      .IO ( ddr_dq[29] ),
      .O ( ddr_dq_I[29] ),
      .T ( ddr_dq_T[29] )
    );

  IOBUF
    iobuf_161 (
      .I ( ddr_dq_O[28] ),
      .IO ( ddr_dq[28] ),
      .O ( ddr_dq_I[28] ),
      .T ( ddr_dq_T[28] )
    );

  IOBUF
    iobuf_162 (
      .I ( ddr_dq_O[27] ),
      .IO ( ddr_dq[27] ),
      .O ( ddr_dq_I[27] ),
      .T ( ddr_dq_T[27] )
    );

  IOBUF
    iobuf_163 (
      .I ( ddr_dq_O[26] ),
      .IO ( ddr_dq[26] ),
      .O ( ddr_dq_I[26] ),
      .T ( ddr_dq_T[26] )
    );

  IOBUF
    iobuf_164 (
      .I ( ddr_dq_O[25] ),
      .IO ( ddr_dq[25] ),
      .O ( ddr_dq_I[25] ),
      .T ( ddr_dq_T[25] )
    );

  IOBUF
    iobuf_165 (
      .I ( ddr_dq_O[24] ),
      .IO ( ddr_dq[24] ),
      .O ( ddr_dq_I[24] ),
      .T ( ddr_dq_T[24] )
    );

  IOBUF
    iobuf_166 (
      .I ( ddr_dq_O[23] ),
      .IO ( ddr_dq[23] ),
      .O ( ddr_dq_I[23] ),
      .T ( ddr_dq_T[23] )
    );

  IOBUF
    iobuf_167 (
      .I ( ddr_dq_O[22] ),
      .IO ( ddr_dq[22] ),
      .O ( ddr_dq_I[22] ),
      .T ( ddr_dq_T[22] )
    );

  IOBUF
    iobuf_168 (
      .I ( ddr_dq_O[21] ),
      .IO ( ddr_dq[21] ),
      .O ( ddr_dq_I[21] ),
      .T ( ddr_dq_T[21] )
    );

  IOBUF
    iobuf_169 (
      .I ( ddr_dq_O[20] ),
      .IO ( ddr_dq[20] ),
      .O ( ddr_dq_I[20] ),
      .T ( ddr_dq_T[20] )
    );

  IOBUF
    iobuf_170 (
      .I ( ddr_dq_O[19] ),
      .IO ( ddr_dq[19] ),
      .O ( ddr_dq_I[19] ),
      .T ( ddr_dq_T[19] )
    );

  IOBUF
    iobuf_171 (
      .I ( ddr_dq_O[18] ),
      .IO ( ddr_dq[18] ),
      .O ( ddr_dq_I[18] ),
      .T ( ddr_dq_T[18] )
    );

  IOBUF
    iobuf_172 (
      .I ( ddr_dq_O[17] ),
      .IO ( ddr_dq[17] ),
      .O ( ddr_dq_I[17] ),
      .T ( ddr_dq_T[17] )
    );

  IOBUF
    iobuf_173 (
      .I ( ddr_dq_O[16] ),
      .IO ( ddr_dq[16] ),
      .O ( ddr_dq_I[16] ),
      .T ( ddr_dq_T[16] )
    );

  IOBUF
    iobuf_174 (
      .I ( ddr_dq_O[15] ),
      .IO ( ddr_dq[15] ),
      .O ( ddr_dq_I[15] ),
      .T ( ddr_dq_T[15] )
    );

  IOBUF
    iobuf_175 (
      .I ( ddr_dq_O[14] ),
      .IO ( ddr_dq[14] ),
      .O ( ddr_dq_I[14] ),
      .T ( ddr_dq_T[14] )
    );

  IOBUF
    iobuf_176 (
      .I ( ddr_dq_O[13] ),
      .IO ( ddr_dq[13] ),
      .O ( ddr_dq_I[13] ),
      .T ( ddr_dq_T[13] )
    );

  IOBUF
    iobuf_177 (
      .I ( ddr_dq_O[12] ),
      .IO ( ddr_dq[12] ),
      .O ( ddr_dq_I[12] ),
      .T ( ddr_dq_T[12] )
    );

  IOBUF
    iobuf_178 (
      .I ( ddr_dq_O[11] ),
      .IO ( ddr_dq[11] ),
      .O ( ddr_dq_I[11] ),
      .T ( ddr_dq_T[11] )
    );

  IOBUF
    iobuf_179 (
      .I ( ddr_dq_O[10] ),
      .IO ( ddr_dq[10] ),
      .O ( ddr_dq_I[10] ),
      .T ( ddr_dq_T[10] )
    );

  IOBUF
    iobuf_180 (
      .I ( ddr_dq_O[9] ),
      .IO ( ddr_dq[9] ),
      .O ( ddr_dq_I[9] ),
      .T ( ddr_dq_T[9] )
    );

  IOBUF
    iobuf_181 (
      .I ( ddr_dq_O[8] ),
      .IO ( ddr_dq[8] ),
      .O ( ddr_dq_I[8] ),
      .T ( ddr_dq_T[8] )
    );

  IOBUF
    iobuf_182 (
      .I ( ddr_dq_O[7] ),
      .IO ( ddr_dq[7] ),
      .O ( ddr_dq_I[7] ),
      .T ( ddr_dq_T[7] )
    );

  IOBUF
    iobuf_183 (
      .I ( ddr_dq_O[6] ),
      .IO ( ddr_dq[6] ),
      .O ( ddr_dq_I[6] ),
      .T ( ddr_dq_T[6] )
    );

  IOBUF
    iobuf_184 (
      .I ( ddr_dq_O[5] ),
      .IO ( ddr_dq[5] ),
      .O ( ddr_dq_I[5] ),
      .T ( ddr_dq_T[5] )
    );

  IOBUF
    iobuf_185 (
      .I ( ddr_dq_O[4] ),
      .IO ( ddr_dq[4] ),
      .O ( ddr_dq_I[4] ),
      .T ( ddr_dq_T[4] )
    );

  IOBUF
    iobuf_186 (
      .I ( ddr_dq_O[3] ),
      .IO ( ddr_dq[3] ),
      .O ( ddr_dq_I[3] ),
      .T ( ddr_dq_T[3] )
    );

  IOBUF
    iobuf_187 (
      .I ( ddr_dq_O[2] ),
      .IO ( ddr_dq[2] ),
      .O ( ddr_dq_I[2] ),
      .T ( ddr_dq_T[2] )
    );

  IOBUF
    iobuf_188 (
      .I ( ddr_dq_O[1] ),
      .IO ( ddr_dq[1] ),
      .O ( ddr_dq_I[1] ),
      .T ( ddr_dq_T[1] )
    );

  IOBUF
    iobuf_189 (
      .I ( ddr_dq_O[0] ),
      .IO ( ddr_dq[0] ),
      .O ( ddr_dq_I[0] ),
      .T ( ddr_dq_T[0] )
    );

  IOBUF
    iobuf_190 (
      .I ( ddr_dqs_O[3] ),
      .IO ( ddr_dqs[3] ),
      .O ( ddr_dqs_I[3] ),
      .T ( ddr_dqs_T[3] )
    );

  IOBUF
    iobuf_191 (
      .I ( ddr_dqs_O[2] ),
      .IO ( ddr_dqs[2] ),
      .O ( ddr_dqs_I[2] ),
      .T ( ddr_dqs_T[2] )
    );

  IOBUF
    iobuf_192 (
      .I ( ddr_dqs_O[1] ),
      .IO ( ddr_dqs[1] ),
      .O ( ddr_dqs_I[1] ),
      .T ( ddr_dqs_T[1] )
    );

  IOBUF
    iobuf_193 (
      .I ( ddr_dqs_O[0] ),
      .IO ( ddr_dqs[0] ),
      .O ( ddr_dqs_I[0] ),
      .T ( ddr_dqs_T[0] )
    );

  OBUF
    obuf_194 (
      .I ( ddr_rasb_OBUF ),
      .O ( ddr_rasb )
    );

  OBUF
    obuf_195 (
      .I ( ddr_web_OBUF ),
      .O ( ddr_web )
    );

  OBUF
    obuf_196 (
      .I ( tft_lcd_b_OBUF[5] ),
      .O ( tft_lcd_b[5] )
    );

  OBUF
    obuf_197 (
      .I ( tft_lcd_b_OBUF[4] ),
      .O ( tft_lcd_b[4] )
    );

  OBUF
    obuf_198 (
      .I ( tft_lcd_b_OBUF[3] ),
      .O ( tft_lcd_b[3] )
    );

  OBUF
    obuf_199 (
      .I ( tft_lcd_b_OBUF[2] ),
      .O ( tft_lcd_b[2] )
    );

  OBUF
    obuf_200 (
      .I ( tft_lcd_b_OBUF[1] ),
      .O ( tft_lcd_b[1] )
    );

  OBUF
    obuf_201 (
      .I ( tft_lcd_b_OBUF[0] ),
      .O ( tft_lcd_b[0] )
    );

  OBUF
    obuf_202 (
      .I ( tft_lcd_clk_OBUF ),
      .O ( tft_lcd_clk )
    );

  OBUF
    obuf_203 (
      .I ( tft_lcd_g_OBUF[5] ),
      .O ( tft_lcd_g[5] )
    );

  OBUF
    obuf_204 (
      .I ( tft_lcd_g_OBUF[4] ),
      .O ( tft_lcd_g[4] )
    );

  OBUF
    obuf_205 (
      .I ( tft_lcd_g_OBUF[3] ),
      .O ( tft_lcd_g[3] )
    );

  OBUF
    obuf_206 (
      .I ( tft_lcd_g_OBUF[2] ),
      .O ( tft_lcd_g[2] )
    );

  OBUF
    obuf_207 (
      .I ( tft_lcd_g_OBUF[1] ),
      .O ( tft_lcd_g[1] )
    );

  OBUF
    obuf_208 (
      .I ( tft_lcd_g_OBUF[0] ),
      .O ( tft_lcd_g[0] )
    );

  OBUF
    obuf_209 (
      .I ( tft_lcd_hsync_OBUF ),
      .O ( tft_lcd_hsync )
    );

  OBUF
    obuf_210 (
      .I ( tft_lcd_r_OBUF[5] ),
      .O ( tft_lcd_r[5] )
    );

  OBUF
    obuf_211 (
      .I ( tft_lcd_r_OBUF[4] ),
      .O ( tft_lcd_r[4] )
    );

  OBUF
    obuf_212 (
      .I ( tft_lcd_r_OBUF[3] ),
      .O ( tft_lcd_r[3] )
    );

  OBUF
    obuf_213 (
      .I ( tft_lcd_r_OBUF[2] ),
      .O ( tft_lcd_r[2] )
    );

  OBUF
    obuf_214 (
      .I ( tft_lcd_r_OBUF[1] ),
      .O ( tft_lcd_r[1] )
    );

  OBUF
    obuf_215 (
      .I ( tft_lcd_r_OBUF[0] ),
      .O ( tft_lcd_r[0] )
    );

  OBUF
    obuf_216 (
      .I ( tft_lcd_vsync_OBUF ),
      .O ( tft_lcd_vsync )
    );

  OBUF
    obuf_217 (
      .I ( opb_error_OBUF ),
      .O ( opb_error )
    );

  OBUF
    obuf_218 (
      .I ( plb_error_OBUF ),
      .O ( plb_error )
    );

  OBUF
    obuf_219 (
      .I ( sram_clk_OBUF ),
      .O ( sram_clk )
    );

  IBUF
    ibuf_220 (
      .I ( sram_clk_fb ),
      .O ( sram_clk_fb_IBUF )
    );

  OBUF
    obuf_221 (
      .I ( flash_a23_OBUF ),
      .O ( flash_a23 )
    );

  OBUF
    obuf_222 (
      .I ( sram_flash_addr_OBUF[22] ),
      .O ( sram_flash_addr[22] )
    );

  OBUF
    obuf_223 (
      .I ( sram_flash_addr_OBUF[21] ),
      .O ( sram_flash_addr[21] )
    );

  OBUF
    obuf_224 (
      .I ( sram_flash_addr_OBUF[20] ),
      .O ( sram_flash_addr[20] )
    );

  OBUF
    obuf_225 (
      .I ( sram_flash_addr_OBUF[19] ),
      .O ( sram_flash_addr[19] )
    );

  OBUF
    obuf_226 (
      .I ( sram_flash_addr_OBUF[18] ),
      .O ( sram_flash_addr[18] )
    );

  OBUF
    obuf_227 (
      .I ( sram_flash_addr_OBUF[17] ),
      .O ( sram_flash_addr[17] )
    );

  OBUF
    obuf_228 (
      .I ( sram_flash_addr_OBUF[16] ),
      .O ( sram_flash_addr[16] )
    );

  OBUF
    obuf_229 (
      .I ( sram_flash_addr_OBUF[15] ),
      .O ( sram_flash_addr[15] )
    );

  OBUF
    obuf_230 (
      .I ( sram_flash_addr_OBUF[14] ),
      .O ( sram_flash_addr[14] )
    );

  OBUF
    obuf_231 (
      .I ( sram_flash_addr_OBUF[13] ),
      .O ( sram_flash_addr[13] )
    );

  OBUF
    obuf_232 (
      .I ( sram_flash_addr_OBUF[12] ),
      .O ( sram_flash_addr[12] )
    );

  OBUF
    obuf_233 (
      .I ( sram_flash_addr_OBUF[11] ),
      .O ( sram_flash_addr[11] )
    );

  OBUF
    obuf_234 (
      .I ( sram_flash_addr_OBUF[10] ),
      .O ( sram_flash_addr[10] )
    );

  OBUF
    obuf_235 (
      .I ( sram_flash_addr_OBUF[9] ),
      .O ( sram_flash_addr[9] )
    );

  OBUF
    obuf_236 (
      .I ( sram_flash_addr_OBUF[8] ),
      .O ( sram_flash_addr[8] )
    );

  OBUF
    obuf_237 (
      .I ( sram_flash_addr_OBUF[7] ),
      .O ( sram_flash_addr[7] )
    );

  OBUF
    obuf_238 (
      .I ( sram_flash_addr_OBUF[6] ),
      .O ( sram_flash_addr[6] )
    );

  OBUF
    obuf_239 (
      .I ( sram_flash_addr_OBUF[5] ),
      .O ( sram_flash_addr[5] )
    );

  OBUF
    obuf_240 (
      .I ( sram_flash_addr_OBUF[4] ),
      .O ( sram_flash_addr[4] )
    );

  OBUF
    obuf_241 (
      .I ( sram_flash_addr_OBUF[3] ),
      .O ( sram_flash_addr[3] )
    );

  OBUF
    obuf_242 (
      .I ( sram_flash_addr_OBUF[2] ),
      .O ( sram_flash_addr[2] )
    );

  OBUF
    obuf_243 (
      .I ( sram_flash_addr_OBUF[1] ),
      .O ( sram_flash_addr[1] )
    );

  OBUF
    obuf_244 (
      .I ( sram_flash_addr_OBUF[0] ),
      .O ( sram_flash_addr[0] )
    );

  IOBUF
    iobuf_245 (
      .I ( sram_flash_data_O[31] ),
      .IO ( sram_flash_data[31] ),
      .O ( sram_flash_data_I[31] ),
      .T ( sram_flash_data_T[31] )
    );

  IOBUF
    iobuf_246 (
      .I ( sram_flash_data_O[30] ),
      .IO ( sram_flash_data[30] ),
      .O ( sram_flash_data_I[30] ),
      .T ( sram_flash_data_T[30] )
    );

  IOBUF
    iobuf_247 (
      .I ( sram_flash_data_O[29] ),
      .IO ( sram_flash_data[29] ),
      .O ( sram_flash_data_I[29] ),
      .T ( sram_flash_data_T[29] )
    );

  IOBUF
    iobuf_248 (
      .I ( sram_flash_data_O[28] ),
      .IO ( sram_flash_data[28] ),
      .O ( sram_flash_data_I[28] ),
      .T ( sram_flash_data_T[28] )
    );

  IOBUF
    iobuf_249 (
      .I ( sram_flash_data_O[27] ),
      .IO ( sram_flash_data[27] ),
      .O ( sram_flash_data_I[27] ),
      .T ( sram_flash_data_T[27] )
    );

  IOBUF
    iobuf_250 (
      .I ( sram_flash_data_O[26] ),
      .IO ( sram_flash_data[26] ),
      .O ( sram_flash_data_I[26] ),
      .T ( sram_flash_data_T[26] )
    );

  IOBUF
    iobuf_251 (
      .I ( sram_flash_data_O[25] ),
      .IO ( sram_flash_data[25] ),
      .O ( sram_flash_data_I[25] ),
      .T ( sram_flash_data_T[25] )
    );

  IOBUF
    iobuf_252 (
      .I ( sram_flash_data_O[24] ),
      .IO ( sram_flash_data[24] ),
      .O ( sram_flash_data_I[24] ),
      .T ( sram_flash_data_T[24] )
    );

  IOBUF
    iobuf_253 (
      .I ( sram_flash_data_O[23] ),
      .IO ( sram_flash_data[23] ),
      .O ( sram_flash_data_I[23] ),
      .T ( sram_flash_data_T[23] )
    );

  IOBUF
    iobuf_254 (
      .I ( sram_flash_data_O[22] ),
      .IO ( sram_flash_data[22] ),
      .O ( sram_flash_data_I[22] ),
      .T ( sram_flash_data_T[22] )
    );

  IOBUF
    iobuf_255 (
      .I ( sram_flash_data_O[21] ),
      .IO ( sram_flash_data[21] ),
      .O ( sram_flash_data_I[21] ),
      .T ( sram_flash_data_T[21] )
    );

  IOBUF
    iobuf_256 (
      .I ( sram_flash_data_O[20] ),
      .IO ( sram_flash_data[20] ),
      .O ( sram_flash_data_I[20] ),
      .T ( sram_flash_data_T[20] )
    );

  IOBUF
    iobuf_257 (
      .I ( sram_flash_data_O[19] ),
      .IO ( sram_flash_data[19] ),
      .O ( sram_flash_data_I[19] ),
      .T ( sram_flash_data_T[19] )
    );

  IOBUF
    iobuf_258 (
      .I ( sram_flash_data_O[18] ),
      .IO ( sram_flash_data[18] ),
      .O ( sram_flash_data_I[18] ),
      .T ( sram_flash_data_T[18] )
    );

  IOBUF
    iobuf_259 (
      .I ( sram_flash_data_O[17] ),
      .IO ( sram_flash_data[17] ),
      .O ( sram_flash_data_I[17] ),
      .T ( sram_flash_data_T[17] )
    );

  IOBUF
    iobuf_260 (
      .I ( sram_flash_data_O[16] ),
      .IO ( sram_flash_data[16] ),
      .O ( sram_flash_data_I[16] ),
      .T ( sram_flash_data_T[16] )
    );

  IOBUF
    iobuf_261 (
      .I ( sram_flash_data_O[15] ),
      .IO ( sram_flash_data[15] ),
      .O ( sram_flash_data_I[15] ),
      .T ( sram_flash_data_T[15] )
    );

  IOBUF
    iobuf_262 (
      .I ( sram_flash_data_O[14] ),
      .IO ( sram_flash_data[14] ),
      .O ( sram_flash_data_I[14] ),
      .T ( sram_flash_data_T[14] )
    );

  IOBUF
    iobuf_263 (
      .I ( sram_flash_data_O[13] ),
      .IO ( sram_flash_data[13] ),
      .O ( sram_flash_data_I[13] ),
      .T ( sram_flash_data_T[13] )
    );

  IOBUF
    iobuf_264 (
      .I ( sram_flash_data_O[12] ),
      .IO ( sram_flash_data[12] ),
      .O ( sram_flash_data_I[12] ),
      .T ( sram_flash_data_T[12] )
    );

  IOBUF
    iobuf_265 (
      .I ( sram_flash_data_O[11] ),
      .IO ( sram_flash_data[11] ),
      .O ( sram_flash_data_I[11] ),
      .T ( sram_flash_data_T[11] )
    );

  IOBUF
    iobuf_266 (
      .I ( sram_flash_data_O[10] ),
      .IO ( sram_flash_data[10] ),
      .O ( sram_flash_data_I[10] ),
      .T ( sram_flash_data_T[10] )
    );

  IOBUF
    iobuf_267 (
      .I ( sram_flash_data_O[9] ),
      .IO ( sram_flash_data[9] ),
      .O ( sram_flash_data_I[9] ),
      .T ( sram_flash_data_T[9] )
    );

  IOBUF
    iobuf_268 (
      .I ( sram_flash_data_O[8] ),
      .IO ( sram_flash_data[8] ),
      .O ( sram_flash_data_I[8] ),
      .T ( sram_flash_data_T[8] )
    );

  IOBUF
    iobuf_269 (
      .I ( sram_flash_data_O[7] ),
      .IO ( sram_flash_data[7] ),
      .O ( sram_flash_data_I[7] ),
      .T ( sram_flash_data_T[7] )
    );

  IOBUF
    iobuf_270 (
      .I ( sram_flash_data_O[6] ),
      .IO ( sram_flash_data[6] ),
      .O ( sram_flash_data_I[6] ),
      .T ( sram_flash_data_T[6] )
    );

  IOBUF
    iobuf_271 (
      .I ( sram_flash_data_O[5] ),
      .IO ( sram_flash_data[5] ),
      .O ( sram_flash_data_I[5] ),
      .T ( sram_flash_data_T[5] )
    );

  IOBUF
    iobuf_272 (
      .I ( sram_flash_data_O[4] ),
      .IO ( sram_flash_data[4] ),
      .O ( sram_flash_data_I[4] ),
      .T ( sram_flash_data_T[4] )
    );

  IOBUF
    iobuf_273 (
      .I ( sram_flash_data_O[3] ),
      .IO ( sram_flash_data[3] ),
      .O ( sram_flash_data_I[3] ),
      .T ( sram_flash_data_T[3] )
    );

  IOBUF
    iobuf_274 (
      .I ( sram_flash_data_O[2] ),
      .IO ( sram_flash_data[2] ),
      .O ( sram_flash_data_I[2] ),
      .T ( sram_flash_data_T[2] )
    );

  IOBUF
    iobuf_275 (
      .I ( sram_flash_data_O[1] ),
      .IO ( sram_flash_data[1] ),
      .O ( sram_flash_data_I[1] ),
      .T ( sram_flash_data_T[1] )
    );

  IOBUF
    iobuf_276 (
      .I ( sram_flash_data_O[0] ),
      .IO ( sram_flash_data[0] ),
      .O ( sram_flash_data_I[0] ),
      .T ( sram_flash_data_T[0] )
    );

  OBUF
    obuf_277 (
      .I ( sram_cen_OBUF ),
      .O ( sram_cen )
    );

  OBUF
    obuf_278 (
      .I ( sram_flash_oe_n_OBUF ),
      .O ( sram_flash_oe_n )
    );

  OBUF
    obuf_279 (
      .I ( sram_flash_we_n_OBUF ),
      .O ( sram_flash_we_n )
    );

  OBUF
    obuf_280 (
      .I ( sram_bw_OBUF[3] ),
      .O ( sram_bw[3] )
    );

  OBUF
    obuf_281 (
      .I ( sram_bw_OBUF[2] ),
      .O ( sram_bw[2] )
    );

  OBUF
    obuf_282 (
      .I ( sram_bw_OBUF[1] ),
      .O ( sram_bw[1] )
    );

  OBUF
    obuf_283 (
      .I ( sram_bw_OBUF[0] ),
      .O ( sram_bw[0] )
    );

  OBUF
    obuf_284 (
      .I ( flash_ce_OBUF ),
      .O ( flash_ce )
    );

  OBUF
    obuf_285 (
      .I ( sram_adv_ld_n_OBUF ),
      .O ( sram_adv_ld_n )
    );

  OBUF
    obuf_286 (
      .I ( sram_mode_OBUF ),
      .O ( sram_mode )
    );

  BUFGP
    bufgp_287 (
      .I ( sysace_clk_in ),
      .O ( sysace_clk_in_BUFGP )
    );

  IBUF
    ibuf_288 (
      .I ( sysace_mpirq ),
      .O ( sysace_mpirq_IBUF )
    );

  OBUF
    obuf_289 (
      .I ( sace_mpce_OBUF ),
      .O ( sace_mpce )
    );

  OBUF
    obuf_290 (
      .I ( usb_hpi_reset_n_OBUF ),
      .O ( usb_hpi_reset_n )
    );

  IBUF
    ibuf_291 (
      .I ( usb_hpi_int ),
      .O ( usb_hpi_int_IBUF )
    );

  OBUF
    obuf_292 (
      .I ( usb_csn_OBUF[0] ),
      .O ( usb_csn )
    );

  OBUF
    obuf_293 (
      .I ( sace_usb_a_OBUF[6] ),
      .O ( sace_usb_a[6] )
    );

  OBUF
    obuf_294 (
      .I ( sace_usb_a_OBUF[5] ),
      .O ( sace_usb_a[5] )
    );

  OBUF
    obuf_295 (
      .I ( sace_usb_a_OBUF[4] ),
      .O ( sace_usb_a[4] )
    );

  OBUF
    obuf_296 (
      .I ( sace_usb_a_OBUF[3] ),
      .O ( sace_usb_a[3] )
    );

  OBUF
    obuf_297 (
      .I ( sace_usb_a_OBUF[2] ),
      .O ( sace_usb_a[2] )
    );

  OBUF
    obuf_298 (
      .I ( sace_usb_a_OBUF[1] ),
      .O ( sace_usb_a[1] )
    );

  OBUF
    obuf_299 (
      .I ( sace_usb_a_OBUF[0] ),
      .O ( sace_usb_a[0] )
    );

  IOBUF
    iobuf_300 (
      .I ( sace_usb_d_O[15] ),
      .IO ( sace_usb_d[15] ),
      .O ( sace_usb_d_I[15] ),
      .T ( sace_usb_d_T[15] )
    );

  IOBUF
    iobuf_301 (
      .I ( sace_usb_d_O[14] ),
      .IO ( sace_usb_d[14] ),
      .O ( sace_usb_d_I[14] ),
      .T ( sace_usb_d_T[14] )
    );

  IOBUF
    iobuf_302 (
      .I ( sace_usb_d_O[13] ),
      .IO ( sace_usb_d[13] ),
      .O ( sace_usb_d_I[13] ),
      .T ( sace_usb_d_T[13] )
    );

  IOBUF
    iobuf_303 (
      .I ( sace_usb_d_O[12] ),
      .IO ( sace_usb_d[12] ),
      .O ( sace_usb_d_I[12] ),
      .T ( sace_usb_d_T[12] )
    );

  IOBUF
    iobuf_304 (
      .I ( sace_usb_d_O[11] ),
      .IO ( sace_usb_d[11] ),
      .O ( sace_usb_d_I[11] ),
      .T ( sace_usb_d_T[11] )
    );

  IOBUF
    iobuf_305 (
      .I ( sace_usb_d_O[10] ),
      .IO ( sace_usb_d[10] ),
      .O ( sace_usb_d_I[10] ),
      .T ( sace_usb_d_T[10] )
    );

  IOBUF
    iobuf_306 (
      .I ( sace_usb_d_O[9] ),
      .IO ( sace_usb_d[9] ),
      .O ( sace_usb_d_I[9] ),
      .T ( sace_usb_d_T[9] )
    );

  IOBUF
    iobuf_307 (
      .I ( sace_usb_d_O[8] ),
      .IO ( sace_usb_d[8] ),
      .O ( sace_usb_d_I[8] ),
      .T ( sace_usb_d_T[8] )
    );

  IOBUF
    iobuf_308 (
      .I ( sace_usb_d_O[7] ),
      .IO ( sace_usb_d[7] ),
      .O ( sace_usb_d_I[7] ),
      .T ( sace_usb_d_T[7] )
    );

  IOBUF
    iobuf_309 (
      .I ( sace_usb_d_O[6] ),
      .IO ( sace_usb_d[6] ),
      .O ( sace_usb_d_I[6] ),
      .T ( sace_usb_d_T[6] )
    );

  IOBUF
    iobuf_310 (
      .I ( sace_usb_d_O[5] ),
      .IO ( sace_usb_d[5] ),
      .O ( sace_usb_d_I[5] ),
      .T ( sace_usb_d_T[5] )
    );

  IOBUF
    iobuf_311 (
      .I ( sace_usb_d_O[4] ),
      .IO ( sace_usb_d[4] ),
      .O ( sace_usb_d_I[4] ),
      .T ( sace_usb_d_T[4] )
    );

  IOBUF
    iobuf_312 (
      .I ( sace_usb_d_O[3] ),
      .IO ( sace_usb_d[3] ),
      .O ( sace_usb_d_I[3] ),
      .T ( sace_usb_d_T[3] )
    );

  IOBUF
    iobuf_313 (
      .I ( sace_usb_d_O[2] ),
      .IO ( sace_usb_d[2] ),
      .O ( sace_usb_d_I[2] ),
      .T ( sace_usb_d_T[2] )
    );

  IOBUF
    iobuf_314 (
      .I ( sace_usb_d_O[1] ),
      .IO ( sace_usb_d[1] ),
      .O ( sace_usb_d_I[1] ),
      .T ( sace_usb_d_T[1] )
    );

  IOBUF
    iobuf_315 (
      .I ( sace_usb_d_O[0] ),
      .IO ( sace_usb_d[0] ),
      .O ( sace_usb_d_I[0] ),
      .T ( sace_usb_d_T[0] )
    );

  OBUF
    obuf_316 (
      .I ( sace_usb_oen_OBUF ),
      .O ( sace_usb_oen )
    );

  OBUF
    obuf_317 (
      .I ( sace_usb_wen_OBUF ),
      .O ( sace_usb_wen )
    );

endmodule

module proc_sys_reset_0_wrapper
  (
    Slowest_sync_clk,
    Ext_Reset_In,
    Aux_Reset_In,
    Core_Reset_Req,
    Chip_Reset_Req,
    System_Reset_Req,
    Dcm_locked,
    Rstc405resetcore,
    Rstc405resetchip,
    Rstc405resetsys,
    Bus_Struct_Reset,
    Peripheral_Reset
  );
  input Slowest_sync_clk;
  input Ext_Reset_In;
  input Aux_Reset_In;
  input Core_Reset_Req;
  input Chip_Reset_Req;
  input System_Reset_Req;
  input Dcm_locked;
  output Rstc405resetcore;
  output Rstc405resetchip;
  output Rstc405resetsys;
  output [0:0] Bus_Struct_Reset;
  output [0:0] Peripheral_Reset;
endmodule

// synthesis attribute box_type of proc_sys_reset_0_wrapper is "black_box";

module clocks_0_wrapper
  (
    sys_clk,
    sysace_clk,
    tft_clk,
    dcm_rst_n,
    plb_clk,
    plb_clk_n,
    plb_clk90,
    plb_clk270,
    opb_clk,
    dcr_clk,
    ddr_fb_clk,
    ddr_fb_clk90,
    ddr_fb_clk270,
    dcm_locked,
    sram_clk,
    sram_clk_fb
  );
  input sys_clk;
  input sysace_clk;
  output tft_clk;
  input dcm_rst_n;
  output plb_clk;
  output plb_clk_n;
  output plb_clk90;
  output plb_clk270;
  output opb_clk;
  output dcr_clk;
  input ddr_fb_clk;
  output ddr_fb_clk90;
  output ddr_fb_clk270;
  output dcm_locked;
  output sram_clk;
  input sram_clk_fb;
endmodule

// synthesis attribute box_type of clocks_0_wrapper is "black_box";

module misc_logic_0_wrapper
  (
    rst_n,
    rst,
    sys_rst_in,
    sys_rst_in_i,
    clk,
    plb_arb_error,
    opb_error,
    plb_error,
    OPB_xferAck,
    OPB_retry,
    OPB_errAck,
    OPB_timeout,
    phy_mii_int_n,
    phy_mii_int,
    ps2_clk_rx_1,
    ps2_clk_rx_2,
    ps2_clk_tx_1,
    ps2_clk_tx_2,
    ps2_d_rx_1,
    ps2_d_rx_2,
    ps2_d_tx_1,
    ps2_d_tx_2,
    sram_oe_n,
    flash_oe_n,
    sram_flash_oe_n,
    usb_hpi_reset_n,
    GPIO2_d_out,
    GPIO2_t_out,
    GPIO2_in,
    iic_scl_int_i,
    iic_scl_int_o,
    iic_scl_int_t,
    iic_sda_int_i,
    iic_sda_int_o,
    iic_sda_int_t,
    usb_addr,
    usb_data_i,
    usb_data_o,
    usb_data_t,
    usb_rdn,
    usb_wrn,
    usb_ce,
    sysace_mpa,
    sysace_mpd_i,
    sysace_mpd_o,
    sysace_mpd_t,
    sysace_mpoe,
    sysace_mpwe,
    sace_usb_a,
    sace_usb_oen,
    sace_usb_wen,
    ps2_mouse_clk_I,
    ps2_mouse_clk_O,
    ps2_mouse_clk_T,
    ps2_mouse_data_I,
    ps2_mouse_data_O,
    ps2_mouse_data_T,
    ps2_keyb_clk_I,
    ps2_keyb_clk_O,
    ps2_keyb_clk_T,
    ps2_keyb_data_I,
    ps2_keyb_data_O,
    ps2_keyb_data_T,
    sda_I,
    sda_O,
    sda_T,
    scl_I,
    scl_O,
    scl_T,
    sace_usb_d_I,
    sace_usb_d_O,
    sace_usb_d_T
  );
  output rst_n;
  input rst;
  input sys_rst_in;
  output sys_rst_in_i;
  input clk;
  input plb_arb_error;
  output opb_error;
  output plb_error;
  input OPB_xferAck;
  input OPB_retry;
  input OPB_errAck;
  input OPB_timeout;
  input phy_mii_int_n;
  output phy_mii_int;
  output ps2_clk_rx_1;
  output ps2_clk_rx_2;
  input ps2_clk_tx_1;
  input ps2_clk_tx_2;
  output ps2_d_rx_1;
  output ps2_d_rx_2;
  input ps2_d_tx_1;
  input ps2_d_tx_2;
  input sram_oe_n;
  input flash_oe_n;
  output sram_flash_oe_n;
  output usb_hpi_reset_n;
  input [26:0] GPIO2_d_out;
  input [26:0] GPIO2_t_out;
  output [26:0] GPIO2_in;
  output iic_scl_int_i;
  input iic_scl_int_o;
  input iic_scl_int_t;
  output iic_sda_int_i;
  input iic_sda_int_o;
  input iic_sda_int_t;
  input [0:31] usb_addr;
  output [0:31] usb_data_i;
  input [0:31] usb_data_o;
  input [0:31] usb_data_t;
  input usb_rdn;
  input usb_wrn;
  input usb_ce;
  input [6:0] sysace_mpa;
  output [15:0] sysace_mpd_i;
  input [15:0] sysace_mpd_o;
  input [15:0] sysace_mpd_t;
  input sysace_mpoe;
  input sysace_mpwe;
  output [6:0] sace_usb_a;
  output sace_usb_oen;
  output sace_usb_wen;
  input ps2_mouse_clk_I;
  output ps2_mouse_clk_O;
  output ps2_mouse_clk_T;
  input ps2_mouse_data_I;
  output ps2_mouse_data_O;
  output ps2_mouse_data_T;
  input ps2_keyb_clk_I;
  output ps2_keyb_clk_O;
  output ps2_keyb_clk_T;
  input ps2_keyb_data_I;
  output ps2_keyb_data_O;
  output ps2_keyb_data_T;
  input sda_I;
  output sda_O;
  output sda_T;
  input scl_I;
  output scl_O;
  output scl_T;
  input [15:0] sace_usb_d_I;
  output [15:0] sace_usb_d_O;
  output [15:0] sace_usb_d_T;
endmodule

// synthesis attribute box_type of misc_logic_0_wrapper is "black_box";

module microblaze_0_wrapper
  (
    CLK,
    RESET,
    INTERRUPT,
    DEBUG_RST,
    EXT_BRK,
    EXT_NM_BRK,
    DBG_STOP,
    INSTR,
    I_ADDRTAG,
    IREADY,
    IWAIT,
    INSTR_ADDR,
    IFETCH,
    I_AS,
    DATA_READ,
    DREADY,
    DWAIT,
    DATA_WRITE,
    DATA_ADDR,
    D_ADDRTAG,
    D_AS,
    READ_STROBE,
    WRITE_STROBE,
    BYTE_ENABLE,
    DM_ABUS,
    DM_BE,
    DM_BUSLOCK,
    DM_DBUS,
    DM_REQUEST,
    DM_RNW,
    DM_SELECT,
    DM_SEQADDR,
    DOPB_DBUS,
    DOPB_ERRACK,
    DOPB_MGRANT,
    DOPB_RETRY,
    DOPB_TIMEOUT,
    DOPB_XFERACK,
    IM_ABUS,
    IM_BE,
    IM_BUSLOCK,
    IM_DBUS,
    IM_REQUEST,
    IM_RNW,
    IM_SELECT,
    IM_SEQADDR,
    IOPB_DBUS,
    IOPB_ERRACK,
    IOPB_MGRANT,
    IOPB_RETRY,
    IOPB_TIMEOUT,
    IOPB_XFERACK,
    DBG_CLK,
    DBG_TDI,
    DBG_TDO,
    DBG_REG_EN,
    DBG_CAPTURE,
    DBG_UPDATE,
    VALID_INSTR,
    PC_EX,
    REG_WRITE,
    REG_ADDR,
    MSR_REG,
    NEW_REG_VALUE,
    PIPE_RUNNING,
    INTERRUPT_TAKEN,
    JUMP_TAKEN,
    PREFETCH_ADDR,
    MB_Halted,
    Trace_Branch_Instr,
    Trace_Delay_Slot,
    Trace_Data_Address,
    Trace_AS,
    Trace_Data_Read,
    Trace_Data_Write,
    Trace_DCache_Req,
    Trace_DCache_Hit,
    Trace_ICache_Req,
    Trace_ICache_Hit,
    Trace_Instr_EX,
    FSL0_S_CLK,
    FSL0_S_READ,
    FSL0_S_DATA,
    FSL0_S_CONTROL,
    FSL0_S_EXISTS,
    FSL0_M_CLK,
    FSL0_M_WRITE,
    FSL0_M_DATA,
    FSL0_M_CONTROL,
    FSL0_M_FULL,
    FSL1_S_CLK,
    FSL1_S_READ,
    FSL1_S_DATA,
    FSL1_S_CONTROL,
    FSL1_S_EXISTS,
    FSL1_M_CLK,
    FSL1_M_WRITE,
    FSL1_M_DATA,
    FSL1_M_CONTROL,
    FSL1_M_FULL,
    FSL2_S_CLK,
    FSL2_S_READ,
    FSL2_S_DATA,
    FSL2_S_CONTROL,
    FSL2_S_EXISTS,
    FSL2_M_CLK,
    FSL2_M_WRITE,
    FSL2_M_DATA,
    FSL2_M_CONTROL,
    FSL2_M_FULL,
    FSL3_S_CLK,
    FSL3_S_READ,
    FSL3_S_DATA,
    FSL3_S_CONTROL,
    FSL3_S_EXISTS,
    FSL3_M_CLK,
    FSL3_M_WRITE,
    FSL3_M_DATA,
    FSL3_M_CONTROL,
    FSL3_M_FULL,
    FSL4_S_CLK,
    FSL4_S_READ,
    FSL4_S_DATA,
    FSL4_S_CONTROL,
    FSL4_S_EXISTS,
    FSL4_M_CLK,
    FSL4_M_WRITE,
    FSL4_M_DATA,
    FSL4_M_CONTROL,
    FSL4_M_FULL,
    FSL5_S_CLK,
    FSL5_S_READ,
    FSL5_S_DATA,
    FSL5_S_CONTROL,
    FSL5_S_EXISTS,
    FSL5_M_CLK,
    FSL5_M_WRITE,
    FSL5_M_DATA,
    FSL5_M_CONTROL,
    FSL5_M_FULL,
    FSL6_S_CLK,
    FSL6_S_READ,
    FSL6_S_DATA,
    FSL6_S_CONTROL,
    FSL6_S_EXISTS,
    FSL6_M_CLK,
    FSL6_M_WRITE,
    FSL6_M_DATA,
    FSL6_M_CONTROL,
    FSL6_M_FULL,
    FSL7_S_CLK,
    FSL7_S_READ,
    FSL7_S_DATA,
    FSL7_S_CONTROL,
    FSL7_S_EXISTS,
    FSL7_M_CLK,
    FSL7_M_WRITE,
    FSL7_M_DATA,
    FSL7_M_CONTROL,
    FSL7_M_FULL
  );
  input CLK;
  input RESET;
  input INTERRUPT;
  input DEBUG_RST;
  input EXT_BRK;
  input EXT_NM_BRK;
  input DBG_STOP;
  input [0:31] INSTR;
  output [0:3] I_ADDRTAG;
  input IREADY;
  input IWAIT;
  output [0:31] INSTR_ADDR;
  output IFETCH;
  output I_AS;
  input [0:31] DATA_READ;
  input DREADY;
  input DWAIT;
  output [0:31] DATA_WRITE;
  output [0:31] DATA_ADDR;
  output [0:3] D_ADDRTAG;
  output D_AS;
  output READ_STROBE;
  output WRITE_STROBE;
  output [0:3] BYTE_ENABLE;
  output [0:31] DM_ABUS;
  output [0:3] DM_BE;
  output DM_BUSLOCK;
  output [0:31] DM_DBUS;
  output DM_REQUEST;
  output DM_RNW;
  output DM_SELECT;
  output DM_SEQADDR;
  input [0:31] DOPB_DBUS;
  input DOPB_ERRACK;
  input DOPB_MGRANT;
  input DOPB_RETRY;
  input DOPB_TIMEOUT;
  input DOPB_XFERACK;
  output [0:31] IM_ABUS;
  output [0:3] IM_BE;
  output IM_BUSLOCK;
  output [0:31] IM_DBUS;
  output IM_REQUEST;
  output IM_RNW;
  output IM_SELECT;
  output IM_SEQADDR;
  input [0:31] IOPB_DBUS;
  input IOPB_ERRACK;
  input IOPB_MGRANT;
  input IOPB_RETRY;
  input IOPB_TIMEOUT;
  input IOPB_XFERACK;
  input DBG_CLK;
  input DBG_TDI;
  output DBG_TDO;
  input [0:4] DBG_REG_EN;
  input DBG_CAPTURE;
  input DBG_UPDATE;
  output VALID_INSTR;
  output [0:31] PC_EX;
  output REG_WRITE;
  output [0:4] REG_ADDR;
  output [0:7] MSR_REG;
  output [0:31] NEW_REG_VALUE;
  output PIPE_RUNNING;
  output INTERRUPT_TAKEN;
  output JUMP_TAKEN;
  output [0:3] PREFETCH_ADDR;
  output MB_Halted;
  output Trace_Branch_Instr;
  output Trace_Delay_Slot;
  output [0:31] Trace_Data_Address;
  output Trace_AS;
  output Trace_Data_Read;
  output Trace_Data_Write;
  output Trace_DCache_Req;
  output Trace_DCache_Hit;
  output Trace_ICache_Req;
  output Trace_ICache_Hit;
  output [0:31] Trace_Instr_EX;
  output FSL0_S_CLK;
  output FSL0_S_READ;
  input [0:31] FSL0_S_DATA;
  input FSL0_S_CONTROL;
  input FSL0_S_EXISTS;
  output FSL0_M_CLK;
  output FSL0_M_WRITE;
  output [0:31] FSL0_M_DATA;
  output FSL0_M_CONTROL;
  input FSL0_M_FULL;
  output FSL1_S_CLK;
  output FSL1_S_READ;
  input [0:31] FSL1_S_DATA;
  input FSL1_S_CONTROL;
  input FSL1_S_EXISTS;
  output FSL1_M_CLK;
  output FSL1_M_WRITE;
  output [0:31] FSL1_M_DATA;
  output FSL1_M_CONTROL;
  input FSL1_M_FULL;
  output FSL2_S_CLK;
  output FSL2_S_READ;
  input [0:31] FSL2_S_DATA;
  input FSL2_S_CONTROL;
  input FSL2_S_EXISTS;
  output FSL2_M_CLK;
  output FSL2_M_WRITE;
  output [0:31] FSL2_M_DATA;
  output FSL2_M_CONTROL;
  input FSL2_M_FULL;
  output FSL3_S_CLK;
  output FSL3_S_READ;
  input [0:31] FSL3_S_DATA;
  input FSL3_S_CONTROL;
  input FSL3_S_EXISTS;
  output FSL3_M_CLK;
  output FSL3_M_WRITE;
  output [0:31] FSL3_M_DATA;
  output FSL3_M_CONTROL;
  input FSL3_M_FULL;
  output FSL4_S_CLK;
  output FSL4_S_READ;
  input [0:31] FSL4_S_DATA;
  input FSL4_S_CONTROL;
  input FSL4_S_EXISTS;
  output FSL4_M_CLK;
  output FSL4_M_WRITE;
  output [0:31] FSL4_M_DATA;
  output FSL4_M_CONTROL;
  input FSL4_M_FULL;
  output FSL5_S_CLK;
  output FSL5_S_READ;
  input [0:31] FSL5_S_DATA;
  input FSL5_S_CONTROL;
  input FSL5_S_EXISTS;
  output FSL5_M_CLK;
  output FSL5_M_WRITE;
  output [0:31] FSL5_M_DATA;
  output FSL5_M_CONTROL;
  input FSL5_M_FULL;
  output FSL6_S_CLK;
  output FSL6_S_READ;
  input [0:31] FSL6_S_DATA;
  input FSL6_S_CONTROL;
  input FSL6_S_EXISTS;
  output FSL6_M_CLK;
  output FSL6_M_WRITE;
  output [0:31] FSL6_M_DATA;
  output FSL6_M_CONTROL;
  input FSL6_M_FULL;
  output FSL7_S_CLK;
  output FSL7_S_READ;
  input [0:31] FSL7_S_DATA;
  input FSL7_S_CONTROL;
  input FSL7_S_EXISTS;
  output FSL7_M_CLK;
  output FSL7_M_WRITE;
  output [0:31] FSL7_M_DATA;
  output FSL7_M_CONTROL;
  input FSL7_M_FULL;
endmodule

// synthesis attribute box_type of microblaze_0_wrapper is "black_box";

module lmb_bram_if_cntlr_0_wrapper
  (
    LMB_Clk,
    LMB_Rst,
    LMB_ABus,
    LMB_WriteDBus,
    LMB_AddrStrobe,
    LMB_ReadStrobe,
    LMB_WriteStrobe,
    LMB_BE,
    Sl_DBus,
    Sl_Ready,
    BRAM_Rst_A,
    BRAM_Clk_A,
    BRAM_EN_A,
    BRAM_WEN_A,
    BRAM_Addr_A,
    BRAM_Din_A,
    BRAM_Dout_A
  );
  input LMB_Clk;
  input LMB_Rst;
  input [0:31] LMB_ABus;
  input [0:31] LMB_WriteDBus;
  input LMB_AddrStrobe;
  input LMB_ReadStrobe;
  input LMB_WriteStrobe;
  input [0:3] LMB_BE;
  output [0:31] Sl_DBus;
  output Sl_Ready;
  output BRAM_Rst_A;
  output BRAM_Clk_A;
  output BRAM_EN_A;
  output [0:3] BRAM_WEN_A;
  output [0:31] BRAM_Addr_A;
  input [0:31] BRAM_Din_A;
  output [0:31] BRAM_Dout_A;
endmodule

// synthesis attribute box_type of lmb_bram_if_cntlr_0_wrapper is "black_box";

module lmb_v10_0_wrapper
  (
    LMB_Clk,
    SYS_Rst,
    LMB_Rst,
    M_ABus,
    M_ReadStrobe,
    M_WriteStrobe,
    M_AddrStrobe,
    M_DBus,
    M_BE,
    Sl_DBus,
    Sl_Ready,
    LMB_ABus,
    LMB_ReadStrobe,
    LMB_WriteStrobe,
    LMB_AddrStrobe,
    LMB_ReadDBus,
    LMB_WriteDBus,
    LMB_Ready,
    LMB_BE
  );
  input LMB_Clk;
  input SYS_Rst;
  output LMB_Rst;
  input [0:31] M_ABus;
  input M_ReadStrobe;
  input M_WriteStrobe;
  input M_AddrStrobe;
  input [0:31] M_DBus;
  input [0:3] M_BE;
  input [0:31] Sl_DBus;
  input [0:0] Sl_Ready;
  output [0:31] LMB_ABus;
  output LMB_ReadStrobe;
  output LMB_WriteStrobe;
  output LMB_AddrStrobe;
  output [0:31] LMB_ReadDBus;
  output [0:31] LMB_WriteDBus;
  output LMB_Ready;
  output [0:3] LMB_BE;
endmodule

// synthesis attribute box_type of lmb_v10_0_wrapper is "black_box";

module lmb_bram_if_cntlr_1_wrapper
  (
    LMB_Clk,
    LMB_Rst,
    LMB_ABus,
    LMB_WriteDBus,
    LMB_AddrStrobe,
    LMB_ReadStrobe,
    LMB_WriteStrobe,
    LMB_BE,
    Sl_DBus,
    Sl_Ready,
    BRAM_Rst_A,
    BRAM_Clk_A,
    BRAM_EN_A,
    BRAM_WEN_A,
    BRAM_Addr_A,
    BRAM_Din_A,
    BRAM_Dout_A
  );
  input LMB_Clk;
  input LMB_Rst;
  input [0:31] LMB_ABus;
  input [0:31] LMB_WriteDBus;
  input LMB_AddrStrobe;
  input LMB_ReadStrobe;
  input LMB_WriteStrobe;
  input [0:3] LMB_BE;
  output [0:31] Sl_DBus;
  output Sl_Ready;
  output BRAM_Rst_A;
  output BRAM_Clk_A;
  output BRAM_EN_A;
  output [0:3] BRAM_WEN_A;
  output [0:31] BRAM_Addr_A;
  input [0:31] BRAM_Din_A;
  output [0:31] BRAM_Dout_A;
endmodule

// synthesis attribute box_type of lmb_bram_if_cntlr_1_wrapper is "black_box";

module lmb_v10_1_wrapper
  (
    LMB_Clk,
    SYS_Rst,
    LMB_Rst,
    M_ABus,
    M_ReadStrobe,
    M_WriteStrobe,
    M_AddrStrobe,
    M_DBus,
    M_BE,
    Sl_DBus,
    Sl_Ready,
    LMB_ABus,
    LMB_ReadStrobe,
    LMB_WriteStrobe,
    LMB_AddrStrobe,
    LMB_ReadDBus,
    LMB_WriteDBus,
    LMB_Ready,
    LMB_BE
  );
  input LMB_Clk;
  input SYS_Rst;
  output LMB_Rst;
  input [0:31] M_ABus;
  input M_ReadStrobe;
  input M_WriteStrobe;
  input M_AddrStrobe;
  input [0:31] M_DBus;
  input [0:3] M_BE;
  input [0:31] Sl_DBus;
  input [0:0] Sl_Ready;
  output [0:31] LMB_ABus;
  output LMB_ReadStrobe;
  output LMB_WriteStrobe;
  output LMB_AddrStrobe;
  output [0:31] LMB_ReadDBus;
  output [0:31] LMB_WriteDBus;
  output LMB_Ready;
  output [0:3] LMB_BE;
endmodule

// synthesis attribute box_type of lmb_v10_1_wrapper is "black_box";

module bram_block_0_wrapper
  (
    BRAM_Rst_A,
    BRAM_Clk_A,
    BRAM_EN_A,
    BRAM_WEN_A,
    BRAM_Addr_A,
    BRAM_Din_A,
    BRAM_Dout_A,
    BRAM_Rst_B,
    BRAM_Clk_B,
    BRAM_EN_B,
    BRAM_WEN_B,
    BRAM_Addr_B,
    BRAM_Din_B,
    BRAM_Dout_B
  );
  input BRAM_Rst_A;
  input BRAM_Clk_A;
  input BRAM_EN_A;
  input [0:3] BRAM_WEN_A;
  input [0:31] BRAM_Addr_A;
  output [0:31] BRAM_Din_A;
  input [0:31] BRAM_Dout_A;
  input BRAM_Rst_B;
  input BRAM_Clk_B;
  input BRAM_EN_B;
  input [0:3] BRAM_WEN_B;
  input [0:31] BRAM_Addr_B;
  output [0:31] BRAM_Din_B;
  input [0:31] BRAM_Dout_B;
endmodule

// synthesis attribute box_type of bram_block_0_wrapper is "black_box";

module opb_v20_0_wrapper
  (
    OPB_Clk,
    OPB_Rst,
    SYS_Rst,
    Debug_SYS_Rst,
    WDT_Rst,
    M_ABus,
    M_BE,
    M_beXfer,
    M_busLock,
    M_DBus,
    M_DBusEn,
    M_DBusEn32_63,
    M_dwXfer,
    M_fwXfer,
    M_hwXfer,
    M_request,
    M_RNW,
    M_select,
    M_seqAddr,
    Sl_beAck,
    Sl_DBus,
    Sl_DBusEn,
    Sl_DBusEn32_63,
    Sl_errAck,
    Sl_dwAck,
    Sl_fwAck,
    Sl_hwAck,
    Sl_retry,
    Sl_toutSup,
    Sl_xferAck,
    OPB_MRequest,
    OPB_ABus,
    OPB_BE,
    OPB_beXfer,
    OPB_beAck,
    OPB_busLock,
    OPB_rdDBus,
    OPB_wrDBus,
    OPB_DBus,
    OPB_errAck,
    OPB_dwAck,
    OPB_dwXfer,
    OPB_fwAck,
    OPB_fwXfer,
    OPB_hwAck,
    OPB_hwXfer,
    OPB_MGrant,
    OPB_pendReq,
    OPB_retry,
    OPB_RNW,
    OPB_select,
    OPB_seqAddr,
    OPB_timeout,
    OPB_toutSup,
    OPB_xferAck
  );
  input OPB_Clk;
  output OPB_Rst;
  input SYS_Rst;
  input Debug_SYS_Rst;
  input WDT_Rst;
  input [0:63] M_ABus;
  input [0:7] M_BE;
  input [0:1] M_beXfer;
  input [0:1] M_busLock;
  input [0:63] M_DBus;
  input [0:1] M_DBusEn;
  input [0:1] M_DBusEn32_63;
  input [0:1] M_dwXfer;
  input [0:1] M_fwXfer;
  input [0:1] M_hwXfer;
  input [0:1] M_request;
  input [0:1] M_RNW;
  input [0:1] M_select;
  input [0:1] M_seqAddr;
  input [0:15] Sl_beAck;
  input [0:511] Sl_DBus;
  input [0:15] Sl_DBusEn;
  input [0:15] Sl_DBusEn32_63;
  input [0:15] Sl_errAck;
  input [0:15] Sl_dwAck;
  input [0:15] Sl_fwAck;
  input [0:15] Sl_hwAck;
  input [0:15] Sl_retry;
  input [0:15] Sl_toutSup;
  input [0:15] Sl_xferAck;
  output [0:1] OPB_MRequest;
  output [0:31] OPB_ABus;
  output [0:3] OPB_BE;
  output OPB_beXfer;
  output OPB_beAck;
  output OPB_busLock;
  output [0:31] OPB_rdDBus;
  output [0:31] OPB_wrDBus;
  output [0:31] OPB_DBus;
  output OPB_errAck;
  output OPB_dwAck;
  output OPB_dwXfer;
  output OPB_fwAck;
  output OPB_fwXfer;
  output OPB_hwAck;
  output OPB_hwXfer;
  output [0:1] OPB_MGrant;
  output [0:1] OPB_pendReq;
  output OPB_retry;
  output OPB_RNW;
  output OPB_select;
  output OPB_seqAddr;
  output OPB_timeout;
  output OPB_toutSup;
  output OPB_xferAck;
endmodule

// synthesis attribute box_type of opb_v20_0_wrapper is "black_box";

module opb_mdm_0_wrapper
  (
    OPB_Clk,
    OPB_Rst,
    Interrupt,
    Debug_SYS_Rst,
    Debug_Rst,
    Ext_BRK,
    Ext_NM_BRK,
    OPB_ABus,
    OPB_BE,
    OPB_RNW,
    OPB_select,
    OPB_seqAddr,
    OPB_DBus,
    MDM_DBus,
    MDM_errAck,
    MDM_retry,
    MDM_toutSup,
    MDM_xferAck,
    Dbg_Clk_0,
    Dbg_TDI_0,
    Dbg_TDO_0,
    Dbg_Reg_En_0,
    Dbg_Capture_0,
    Dbg_Update_0,
    Dbg_Clk_1,
    Dbg_TDI_1,
    Dbg_TDO_1,
    Dbg_Reg_En_1,
    Dbg_Capture_1,
    Dbg_Update_1,
    Dbg_Clk_2,
    Dbg_TDI_2,
    Dbg_TDO_2,
    Dbg_Reg_En_2,
    Dbg_Capture_2,
    Dbg_Update_2,
    Dbg_Clk_3,
    Dbg_TDI_3,
    Dbg_TDO_3,
    Dbg_Reg_En_3,
    Dbg_Capture_3,
    Dbg_Update_3,
    Dbg_Clk_4,
    Dbg_TDI_4,
    Dbg_TDO_4,
    Dbg_Reg_En_4,
    Dbg_Capture_4,
    Dbg_Update_4,
    Dbg_Clk_5,
    Dbg_TDI_5,
    Dbg_TDO_5,
    Dbg_Reg_En_5,
    Dbg_Capture_5,
    Dbg_Update_5,
    Dbg_Clk_6,
    Dbg_TDI_6,
    Dbg_TDO_6,
    Dbg_Reg_En_6,
    Dbg_Capture_6,
    Dbg_Update_6,
    Dbg_Clk_7,
    Dbg_TDI_7,
    Dbg_TDO_7,
    Dbg_Reg_En_7,
    Dbg_Capture_7,
    Dbg_Update_7,
    bscan_tdi,
    bscan_reset,
    bscan_shift,
    bscan_update,
    bscan_capture,
    bscan_sel1,
    bscan_drck1,
    bscan_tdo1,
    FSL0_S_CLK,
    FSL0_S_READ,
    FSL0_S_DATA,
    FSL0_S_CONTROL,
    FSL0_S_EXISTS,
    FSL0_M_CLK,
    FSL0_M_WRITE,
    FSL0_M_DATA,
    FSL0_M_CONTROL,
    FSL0_M_FULL
  );
  input OPB_Clk;
  input OPB_Rst;
  output Interrupt;
  output Debug_SYS_Rst;
  output Debug_Rst;
  output Ext_BRK;
  output Ext_NM_BRK;
  input [0:31] OPB_ABus;
  input [0:3] OPB_BE;
  input OPB_RNW;
  input OPB_select;
  input OPB_seqAddr;
  input [0:31] OPB_DBus;
  output [0:31] MDM_DBus;
  output MDM_errAck;
  output MDM_retry;
  output MDM_toutSup;
  output MDM_xferAck;
  output Dbg_Clk_0;
  output Dbg_TDI_0;
  input Dbg_TDO_0;
  output [0:4] Dbg_Reg_En_0;
  output Dbg_Capture_0;
  output Dbg_Update_0;
  output Dbg_Clk_1;
  output Dbg_TDI_1;
  input Dbg_TDO_1;
  output [0:4] Dbg_Reg_En_1;
  output Dbg_Capture_1;
  output Dbg_Update_1;
  output Dbg_Clk_2;
  output Dbg_TDI_2;
  input Dbg_TDO_2;
  output [0:4] Dbg_Reg_En_2;
  output Dbg_Capture_2;
  output Dbg_Update_2;
  output Dbg_Clk_3;
  output Dbg_TDI_3;
  input Dbg_TDO_3;
  output [0:4] Dbg_Reg_En_3;
  output Dbg_Capture_3;
  output Dbg_Update_3;
  output Dbg_Clk_4;
  output Dbg_TDI_4;
  input Dbg_TDO_4;
  output [0:4] Dbg_Reg_En_4;
  output Dbg_Capture_4;
  output Dbg_Update_4;
  output Dbg_Clk_5;
  output Dbg_TDI_5;
  input Dbg_TDO_5;
  output [0:4] Dbg_Reg_En_5;
  output Dbg_Capture_5;
  output Dbg_Update_5;
  output Dbg_Clk_6;
  output Dbg_TDI_6;
  input Dbg_TDO_6;
  output [0:4] Dbg_Reg_En_6;
  output Dbg_Capture_6;
  output Dbg_Update_6;
  output Dbg_Clk_7;
  output Dbg_TDI_7;
  input Dbg_TDO_7;
  output [0:4] Dbg_Reg_En_7;
  output Dbg_Capture_7;
  output Dbg_Update_7;
  output bscan_tdi;
  output bscan_reset;
  output bscan_shift;
  output bscan_update;
  output bscan_capture;
  output bscan_sel1;
  output bscan_drck1;
  input bscan_tdo1;
  output FSL0_S_CLK;
  output FSL0_S_READ;
  input [0:31] FSL0_S_DATA;
  input FSL0_S_CONTROL;
  input FSL0_S_EXISTS;
  output FSL0_M_CLK;
  output FSL0_M_WRITE;
  output [0:31] FSL0_M_DATA;
  output FSL0_M_CONTROL;
  input FSL0_M_FULL;
endmodule

// synthesis attribute box_type of opb_mdm_0_wrapper is "black_box";

module opb_intc_0_wrapper
  (
    OPB_Clk,
    Intr,
    OPB_Rst,
    OPB_ABus,
    OPB_BE,
    OPB_RNW,
    OPB_select,
    OPB_seqAddr,
    OPB_DBus,
    IntC_DBus,
    IntC_errAck,
    IntC_retry,
    IntC_toutSup,
    IntC_xferAck,
    Irq
  );
  input OPB_Clk;
  input [10:0] Intr;
  input OPB_Rst;
  input [0:31] OPB_ABus;
  input [0:3] OPB_BE;
  input OPB_RNW;
  input OPB_select;
  input OPB_seqAddr;
  input [0:31] OPB_DBus;
  output [0:31] IntC_DBus;
  output IntC_errAck;
  output IntC_retry;
  output IntC_toutSup;
  output IntC_xferAck;
  output Irq;
endmodule

// synthesis attribute box_type of opb_intc_0_wrapper is "black_box";

module opb_timer_0_wrapper
  (
    OPB_Clk,
    OPB_Rst,
    OPB_ABus,
    OPB_BE,
    OPB_DBus,
    OPB_RNW,
    OPB_select,
    OPB_seqAddr,
    TC_DBus,
    TC_errAck,
    TC_retry,
    TC_toutSup,
    TC_xferAck,
    CaptureTrig0,
    CaptureTrig1,
    GenerateOut0,
    GenerateOut1,
    PWM0,
    Interrupt,
    Freeze
  );
  input OPB_Clk;
  input OPB_Rst;
  input [0:31] OPB_ABus;
  input [0:3] OPB_BE;
  input [0:31] OPB_DBus;
  input OPB_RNW;
  input OPB_select;
  input OPB_seqAddr;
  output [0:31] TC_DBus;
  output TC_errAck;
  output TC_retry;
  output TC_toutSup;
  output TC_xferAck;
  input CaptureTrig0;
  input CaptureTrig1;
  output GenerateOut0;
  output GenerateOut1;
  output PWM0;
  output Interrupt;
  input Freeze;
endmodule

// synthesis attribute box_type of opb_timer_0_wrapper is "black_box";

module opb_uart16550_0_wrapper
  (
    OPB_Clk,
    OPB_Rst,
    IP2INTC_Irpt,
    Freeze,
    OPB_ABus,
    OPB_BE,
    OPB_RNW,
    OPB_select,
    OPB_seqAddr,
    OPB_DBus,
    Sln_DBus,
    Sln_ErrAck,
    Sln_Retry,
    Sln_ToutSup,
    Sln_XferAck,
    baudoutN,
    ctsN,
    dcdN,
    ddis,
    dsrN,
    dtrN,
    out1N,
    out2N,
    rclk,
    riN,
    rtsN,
    rxrdyN,
    sin,
    sout,
    txrdyN,
    xin,
    xout
  );
  input OPB_Clk;
  input OPB_Rst;
  output IP2INTC_Irpt;
  input Freeze;
  input [0:31] OPB_ABus;
  input [0:3] OPB_BE;
  input OPB_RNW;
  input OPB_select;
  input OPB_seqAddr;
  input [0:31] OPB_DBus;
  output [0:31] Sln_DBus;
  output Sln_ErrAck;
  output Sln_Retry;
  output Sln_ToutSup;
  output Sln_XferAck;
  output baudoutN;
  input ctsN;
  input dcdN;
  output ddis;
  input dsrN;
  output dtrN;
  output out1N;
  output out2N;
  input rclk;
  input riN;
  output rtsN;
  output rxrdyN;
  input sin;
  output sout;
  output txrdyN;
  input xin;
  output xout;
endmodule

// synthesis attribute box_type of opb_uart16550_0_wrapper is "black_box";

module opb_gpio_0_wrapper
  (
    OPB_ABus,
    OPB_BE,
    OPB_Clk,
    OPB_DBus,
    OPB_RNW,
    OPB_Rst,
    OPB_select,
    OPB_seqAddr,
    Sln_DBus,
    Sln_errAck,
    Sln_retry,
    Sln_toutSup,
    Sln_xferAck,
    IP2INTC_Irpt,
    GPIO_in,
    GPIO_d_out,
    GPIO_t_out,
    GPIO2_in,
    GPIO2_d_out,
    GPIO2_t_out,
    GPIO_IO_I,
    GPIO_IO_O,
    GPIO_IO_T,
    GPIO2_IO_I,
    GPIO2_IO_O,
    GPIO2_IO_T
  );
  input [0:31] OPB_ABus;
  input [0:3] OPB_BE;
  input OPB_Clk;
  input [0:31] OPB_DBus;
  input OPB_RNW;
  input OPB_Rst;
  input OPB_select;
  input OPB_seqAddr;
  output [0:31] Sln_DBus;
  output Sln_errAck;
  output Sln_retry;
  output Sln_toutSup;
  output Sln_xferAck;
  output IP2INTC_Irpt;
  input [0:26] GPIO_in;
  output [0:26] GPIO_d_out;
  output [0:26] GPIO_t_out;
  input [0:26] GPIO2_in;
  output [0:26] GPIO2_d_out;
  output [0:26] GPIO2_t_out;
  input [0:26] GPIO_IO_I;
  output [0:26] GPIO_IO_O;
  output [0:26] GPIO_IO_T;
  input [0:26] GPIO2_IO_I;
  output [0:26] GPIO2_IO_O;
  output [0:26] GPIO2_IO_T;
endmodule

// synthesis attribute box_type of opb_gpio_0_wrapper is "black_box";

module opb_ps2_dual_ref_0_wrapper
  (
    OPB_BE,
    IPIF_Rst,
    OPB_Select,
    OPB_DBus,
    OPB_Clk,
    OPB_ABus,
    OPB_RNW,
    OPB_seqAddr,
    Sys_Intr1,
    Sys_Intr2,
    Sln_XferAck,
    Sln_DBus,
    Sln_DBusEn,
    Sln_errAck,
    Sln_retry,
    Sln_toutSup,
    Clkin1,
    Clkpd1,
    Rx1,
    Txpd1,
    Clkin2,
    Clkpd2,
    Rx2,
    Txpd2
  );
  input [0:3] OPB_BE;
  input IPIF_Rst;
  input OPB_Select;
  input [0:31] OPB_DBus;
  input OPB_Clk;
  input [0:31] OPB_ABus;
  input OPB_RNW;
  input OPB_seqAddr;
  output Sys_Intr1;
  output Sys_Intr2;
  output Sln_XferAck;
  output [0:31] Sln_DBus;
  output Sln_DBusEn;
  output Sln_errAck;
  output Sln_retry;
  output Sln_toutSup;
  input Clkin1;
  output Clkpd1;
  input Rx1;
  output Txpd1;
  input Clkin2;
  output Clkpd2;
  input Rx2;
  output Txpd2;
endmodule

// synthesis attribute box_type of opb_ps2_dual_ref_0_wrapper is "black_box";

module opb_iic_0_wrapper
  (
    OPB_Clk,
    Sda_I,
    Sda_O,
    Sda_T,
    Scl_I,
    Scl_O,
    Scl_T,
    Gpo,
    OPB_ABus,
    OPB_DBus,
    Sln_DBus,
    OPB_select,
    OPB_RNW,
    Sln_xferAck,
    Sln_errAck,
    Sln_toutSup,
    Sln_retry,
    IP2INTC_Irpt,
    OPB_Rst,
    Freeze,
    OPB_seqAddr,
    OPB_BE
  );
  input OPB_Clk;
  input Sda_I;
  output Sda_O;
  output Sda_T;
  input Scl_I;
  output Scl_O;
  output Scl_T;
  output [31:31] Gpo;
  input [0:31] OPB_ABus;
  input [0:31] OPB_DBus;
  output [0:31] Sln_DBus;
  input OPB_select;
  input OPB_RNW;
  output Sln_xferAck;
  output Sln_errAck;
  output Sln_toutSup;
  output Sln_retry;
  output IP2INTC_Irpt;
  input OPB_Rst;
  input Freeze;
  input OPB_seqAddr;
  input [0:3] OPB_BE;
endmodule

// synthesis attribute box_type of opb_iic_0_wrapper is "black_box";

module opb_ac97_controller_ref_0_wrapper
  (
    OPB_Clk,
    OPB_Rst,
    OPB_ABus,
    OPB_BE,
    OPB_RNW,
    OPB_select,
    OPB_seqAddr,
    OPB_DBus,
    opb_ac97_controller_DBus,
    opb_ac97_controller_errAck,
    opb_ac97_controller_retry,
    opb_ac97_controller_toutSup,
    opb_ac97_controller_xferAck,
    Playback_Interrupt,
    Record_Interrupt,
    Bit_Clk,
    Sync,
    SData_Out,
    SData_In
  );
  input OPB_Clk;
  input OPB_Rst;
  input [0:31] OPB_ABus;
  input [0:3] OPB_BE;
  input OPB_RNW;
  input OPB_select;
  input OPB_seqAddr;
  input [0:31] OPB_DBus;
  output [0:31] opb_ac97_controller_DBus;
  output opb_ac97_controller_errAck;
  output opb_ac97_controller_retry;
  output opb_ac97_controller_toutSup;
  output opb_ac97_controller_xferAck;
  output Playback_Interrupt;
  output Record_Interrupt;
  input Bit_Clk;
  output Sync;
  output SData_Out;
  input SData_In;
endmodule

// synthesis attribute box_type of opb_ac97_controller_ref_0_wrapper is "black_box";

module plb_v34_0_wrapper
  (
    PLB_Clk,
    SYS_Rst,
    PLB_Rst,
    PLB_dcrAck,
    PLB_dcrDBus,
    DCR_ABus,
    DCR_DBus,
    DCR_Read,
    DCR_Write,
    M_ABus,
    M_BE,
    M_RNW,
    M_abort,
    M_busLock,
    M_compress,
    M_guarded,
    M_lockErr,
    M_MSize,
    M_ordered,
    M_priority,
    M_rdBurst,
    M_request,
    M_size,
    M_type,
    M_wrBurst,
    M_wrDBus,
    Sl_addrAck,
    Sl_MErr,
    Sl_MBusy,
    Sl_rdBTerm,
    Sl_rdComp,
    Sl_rdDAck,
    Sl_rdDBus,
    Sl_rdWdAddr,
    Sl_rearbitrate,
    Sl_SSize,
    Sl_wait,
    Sl_wrBTerm,
    Sl_wrComp,
    Sl_wrDAck,
    PLB_ABus,
    PLB_BE,
    PLB_MAddrAck,
    PLB_MBusy,
    PLB_MErr,
    PLB_MRdBTerm,
    PLB_MRdDAck,
    PLB_MRdDBus,
    PLB_MRdWdAddr,
    PLB_MRearbitrate,
    PLB_MWrBTerm,
    PLB_MWrDAck,
    PLB_MSSize,
    PLB_PAValid,
    PLB_RNW,
    PLB_SAValid,
    PLB_abort,
    PLB_busLock,
    PLB_compress,
    PLB_guarded,
    PLB_lockErr,
    PLB_masterID,
    PLB_MSize,
    PLB_ordered,
    PLB_pendPri,
    PLB_pendReq,
    PLB_rdBurst,
    PLB_rdPrim,
    PLB_reqPri,
    PLB_size,
    PLB_type,
    PLB_wrBurst,
    PLB_wrDBus,
    PLB_wrPrim,
    PLB_SaddrAck,
    PLB_SMErr,
    PLB_SMBusy,
    PLB_SrdBTerm,
    PLB_SrdComp,
    PLB_SrdDAck,
    PLB_SrdDBus,
    PLB_SrdWdAddr,
    PLB_Srearbitrate,
    PLB_Sssize,
    PLB_Swait,
    PLB_SwrBTerm,
    PLB_SwrComp,
    PLB_SwrDAck,
    PLB2OPB_rearb,
    ArbAddrVldReg,
    Bus_Error_Det
  );
  input PLB_Clk;
  input SYS_Rst;
  output PLB_Rst;
  output PLB_dcrAck;
  output [0:31] PLB_dcrDBus;
  input [0:9] DCR_ABus;
  input [0:31] DCR_DBus;
  input DCR_Read;
  input DCR_Write;
  input [0:63] M_ABus;
  input [0:15] M_BE;
  input [0:1] M_RNW;
  input [0:1] M_abort;
  input [0:1] M_busLock;
  input [0:1] M_compress;
  input [0:1] M_guarded;
  input [0:1] M_lockErr;
  input [0:3] M_MSize;
  input [0:1] M_ordered;
  input [0:3] M_priority;
  input [0:1] M_rdBurst;
  input [0:1] M_request;
  input [0:7] M_size;
  input [0:5] M_type;
  input [0:1] M_wrBurst;
  input [0:127] M_wrDBus;
  input [0:0] Sl_addrAck;
  input [0:1] Sl_MErr;
  input [0:1] Sl_MBusy;
  input [0:0] Sl_rdBTerm;
  input [0:0] Sl_rdComp;
  input [0:0] Sl_rdDAck;
  input [0:63] Sl_rdDBus;
  input [0:3] Sl_rdWdAddr;
  input [0:0] Sl_rearbitrate;
  input [0:1] Sl_SSize;
  input [0:0] Sl_wait;
  input [0:0] Sl_wrBTerm;
  input [0:0] Sl_wrComp;
  input [0:0] Sl_wrDAck;
  output [0:31] PLB_ABus;
  output [0:7] PLB_BE;
  output [0:1] PLB_MAddrAck;
  output [0:1] PLB_MBusy;
  output [0:1] PLB_MErr;
  output [0:1] PLB_MRdBTerm;
  output [0:1] PLB_MRdDAck;
  output [0:127] PLB_MRdDBus;
  output [0:7] PLB_MRdWdAddr;
  output [0:1] PLB_MRearbitrate;
  output [0:1] PLB_MWrBTerm;
  output [0:1] PLB_MWrDAck;
  output [0:3] PLB_MSSize;
  output PLB_PAValid;
  output PLB_RNW;
  output PLB_SAValid;
  output PLB_abort;
  output PLB_busLock;
  output PLB_compress;
  output PLB_guarded;
  output PLB_lockErr;
  output [0:0] PLB_masterID;
  output [0:1] PLB_MSize;
  output PLB_ordered;
  output [0:1] PLB_pendPri;
  output PLB_pendReq;
  output PLB_rdBurst;
  output PLB_rdPrim;
  output [0:1] PLB_reqPri;
  output [0:3] PLB_size;
  output [0:2] PLB_type;
  output PLB_wrBurst;
  output [0:63] PLB_wrDBus;
  output PLB_wrPrim;
  output PLB_SaddrAck;
  output [0:1] PLB_SMErr;
  output [0:1] PLB_SMBusy;
  output PLB_SrdBTerm;
  output PLB_SrdComp;
  output PLB_SrdDAck;
  output [0:63] PLB_SrdDBus;
  output [0:3] PLB_SrdWdAddr;
  output PLB_Srearbitrate;
  output [0:1] PLB_Sssize;
  output PLB_Swait;
  output PLB_SwrBTerm;
  output PLB_SwrComp;
  output PLB_SwrDAck;
  input [0:0] PLB2OPB_rearb;
  output ArbAddrVldReg;
  output Bus_Error_Det;
endmodule

// synthesis attribute box_type of plb_v34_0_wrapper is "black_box";

module dcr_v29_0_wrapper
  (
    M_dcrABus,
    M_dcrDBus,
    M_dcrRead,
    M_dcrWrite,
    DCR_M_DBus,
    DCR_Ack,
    DCR_ABus,
    DCR_Sl_DBus,
    DCR_Read,
    DCR_Write,
    Sl_dcrDBus,
    Sl_dcrAck
  );
  input [0:9] M_dcrABus;
  input [0:31] M_dcrDBus;
  input M_dcrRead;
  input M_dcrWrite;
  output [0:31] DCR_M_DBus;
  output DCR_Ack;
  output [0:19] DCR_ABus;
  output [0:63] DCR_Sl_DBus;
  output [0:1] DCR_Read;
  output [0:1] DCR_Write;
  input [0:63] Sl_dcrDBus;
  input [0:1] Sl_dcrAck;
endmodule

// synthesis attribute box_type of dcr_v29_0_wrapper is "black_box";

module opb2dcr_bridge_0_wrapper
  (
    OPB_Clk,
    OPB_Rst,
    OPB_dcrClk,
    OPB_dcrRst,
    OPB_ABus,
    OPB_BE,
    OPB_DBus,
    OPB_RNW,
    OPB_select,
    OPB_seqAddr,
    OPB_xferAck,
    OPB_errAck,
    OPB_retry,
    OPB_timeout,
    Sln_DBus,
    Sln_ErrAck,
    Sln_Retry,
    Sln_ToutSup,
    Sln_XferAck,
    DCR_opbAck,
    DCR_opbDBusIn,
    OPB_dcrRead,
    OPB_dcrWrite,
    OPB_dcrABus,
    OPB_dcrDBusOut
  );
  input OPB_Clk;
  input OPB_Rst;
  output OPB_dcrClk;
  output OPB_dcrRst;
  input [0:31] OPB_ABus;
  input [0:3] OPB_BE;
  input [0:31] OPB_DBus;
  input OPB_RNW;
  input OPB_select;
  input OPB_seqAddr;
  input OPB_xferAck;
  input OPB_errAck;
  input OPB_retry;
  input OPB_timeout;
  output [0:31] Sln_DBus;
  output Sln_ErrAck;
  output Sln_Retry;
  output Sln_ToutSup;
  output Sln_XferAck;
  input DCR_opbAck;
  input [0:31] DCR_opbDBusIn;
  output OPB_dcrRead;
  output OPB_dcrWrite;
  output [0:9] OPB_dcrABus;
  output [0:31] OPB_dcrDBusOut;
endmodule

// synthesis attribute box_type of opb2dcr_bridge_0_wrapper is "black_box";

module opb2plb_bridge_0_wrapper
  (
    OPB_Clk,
    PLB_Clk,
    OPB_Rst,
    PLB_Rst,
    BGI_Trans_Abort,
    Bus_Error_Det,
    OPB_select,
    OPB_ABus,
    OPB_RNW,
    OPB_BE,
    OPB_DBus,
    OPB_seqAddr,
    BGI_DBus,
    BGI_retry,
    BGI_toutSup,
    BGI_xferAck,
    BGI_errAck,
    BGI_request,
    BGI_ABus,
    BGI_RNW,
    BGI_BE,
    BGI_size,
    BGI_type,
    BGI_priority,
    BGI_rdBurst,
    BGI_wrBurst,
    BGI_busLock,
    BGI_abort,
    BGI_lockErr,
    BGI_mSize,
    BGI_ordered,
    BGI_compress,
    BGI_guarded,
    BGI_wrDBus,
    PLB_RdWdAddr,
    PLB_RdDBus,
    PLB_AddrAck,
    PLB_RdDAck,
    PLB_WrDAck,
    PLB_rearbitrate,
    PLB_Busy,
    PLB_Err,
    PLB_RdBTerm,
    PLB_WrBTerm,
    PLB_sSize,
    PLB_pendReq,
    PLB_pendPri,
    PLB_reqPri,
    DCR_Read,
    DCR_Write,
    DCR_ABus,
    DCR_DBus,
    BGI_dcr_DBus,
    BGI_ack
  );
  input OPB_Clk;
  input PLB_Clk;
  input OPB_Rst;
  input PLB_Rst;
  input BGI_Trans_Abort;
  output Bus_Error_Det;
  input OPB_select;
  input [0:31] OPB_ABus;
  input OPB_RNW;
  input [0:3] OPB_BE;
  input [0:31] OPB_DBus;
  input OPB_seqAddr;
  output [0:31] BGI_DBus;
  output BGI_retry;
  output BGI_toutSup;
  output BGI_xferAck;
  output BGI_errAck;
  output BGI_request;
  output [0:31] BGI_ABus;
  output BGI_RNW;
  output [0:7] BGI_BE;
  output [0:3] BGI_size;
  output [0:2] BGI_type;
  output [0:1] BGI_priority;
  output BGI_rdBurst;
  output BGI_wrBurst;
  output BGI_busLock;
  output BGI_abort;
  output BGI_lockErr;
  output [0:1] BGI_mSize;
  output BGI_ordered;
  output BGI_compress;
  output BGI_guarded;
  output [0:63] BGI_wrDBus;
  input [0:3] PLB_RdWdAddr;
  input [0:63] PLB_RdDBus;
  input PLB_AddrAck;
  input PLB_RdDAck;
  input PLB_WrDAck;
  input PLB_rearbitrate;
  input PLB_Busy;
  input PLB_Err;
  input PLB_RdBTerm;
  input PLB_WrBTerm;
  input [0:1] PLB_sSize;
  input PLB_pendReq;
  input [0:1] PLB_pendPri;
  input [0:1] PLB_reqPri;
  input DCR_Read;
  input DCR_Write;
  input [0:9] DCR_ABus;
  input [0:31] DCR_DBus;
  output [0:31] BGI_dcr_DBus;
  output BGI_ack;
endmodule

// synthesis attribute box_type of opb2plb_bridge_0_wrapper is "black_box";

module plb_ddr_0_wrapper
  (
    PLB_Clk,
    PLB_Clk_n,
    Clk90_in,
    Clk90_in_n,
    DDR_Clk90_in,
    DDR_Clk90_in_n,
    PLB_Rst,
    PLB_ABus,
    PLB_PAValid,
    PLB_SAValid,
    PLB_rdPrim,
    PLB_wrPrim,
    PLB_masterID,
    PLB_abort,
    PLB_busLock,
    PLB_RNW,
    PLB_BE,
    PLB_MSize,
    PLB_size,
    PLB_type,
    PLB_compress,
    PLB_guarded,
    PLB_ordered,
    PLB_lockErr,
    PLB_wrDBus,
    PLB_wrBurst,
    PLB_rdBurst,
    PLB_pendReq,
    PLB_pendPri,
    PLB_reqPri,
    Sl_addrAck,
    Sl_SSize,
    Sl_wait,
    Sl_rearbitrate,
    Sl_wrDAck,
    Sl_wrComp,
    Sl_wrBTerm,
    Sl_rdDBus,
    Sl_rdWdAddr,
    Sl_rdDAck,
    Sl_rdComp,
    Sl_rdBTerm,
    Sl_MBusy,
    Sl_MErr,
    IP2INTC_Irpt,
    DDR_Clk,
    DDR_Clkn,
    DDR_CKE,
    DDR_CSn,
    DDR_RASn,
    DDR_CASn,
    DDR_WEn,
    DDR_DM,
    DDR_BankAddr,
    DDR_Addr,
    DDR_DM_ECC,
    DDR_Init_done,
    DDR_DQ_I,
    DDR_DQ_O,
    DDR_DQ_T,
    DDR_DQS_I,
    DDR_DQS_O,
    DDR_DQS_T,
    DDR_DQ_ECC_I,
    DDR_DQ_ECC_O,
    DDR_DQ_ECC_T,
    DDR_DQS_ECC_I,
    DDR_DQS_ECC_O,
    DDR_DQS_ECC_T
  );
  input PLB_Clk;
  input PLB_Clk_n;
  input Clk90_in;
  input Clk90_in_n;
  input DDR_Clk90_in;
  input DDR_Clk90_in_n;
  input PLB_Rst;
  input [0:31] PLB_ABus;
  input PLB_PAValid;
  input PLB_SAValid;
  input PLB_rdPrim;
  input PLB_wrPrim;
  input [0:0] PLB_masterID;
  input PLB_abort;
  input PLB_busLock;
  input PLB_RNW;
  input [0:7] PLB_BE;
  input [0:1] PLB_MSize;
  input [0:3] PLB_size;
  input [0:2] PLB_type;
  input PLB_compress;
  input PLB_guarded;
  input PLB_ordered;
  input PLB_lockErr;
  input [0:63] PLB_wrDBus;
  input PLB_wrBurst;
  input PLB_rdBurst;
  input PLB_pendReq;
  input [0:1] PLB_pendPri;
  input [0:1] PLB_reqPri;
  output Sl_addrAck;
  output [0:1] Sl_SSize;
  output Sl_wait;
  output Sl_rearbitrate;
  output Sl_wrDAck;
  output Sl_wrComp;
  output Sl_wrBTerm;
  output [0:63] Sl_rdDBus;
  output [0:3] Sl_rdWdAddr;
  output Sl_rdDAck;
  output Sl_rdComp;
  output Sl_rdBTerm;
  output [0:1] Sl_MBusy;
  output [0:1] Sl_MErr;
  output IP2INTC_Irpt;
  output [0:0] DDR_Clk;
  output [0:0] DDR_Clkn;
  output [0:0] DDR_CKE;
  output [0:0] DDR_CSn;
  output DDR_RASn;
  output DDR_CASn;
  output DDR_WEn;
  output [0:3] DDR_DM;
  output [0:1] DDR_BankAddr;
  output [0:12] DDR_Addr;
  output DDR_DM_ECC;
  output DDR_Init_done;
  input [0:31] DDR_DQ_I;
  output [0:31] DDR_DQ_O;
  output [0:31] DDR_DQ_T;
  input [0:3] DDR_DQS_I;
  output [0:3] DDR_DQS_O;
  output [0:3] DDR_DQS_T;
  input [0:6] DDR_DQ_ECC_I;
  output [0:6] DDR_DQ_ECC_O;
  output [0:6] DDR_DQ_ECC_T;
  input DDR_DQS_ECC_I;
  output DDR_DQS_ECC_O;
  output DDR_DQS_ECC_T;
endmodule

// synthesis attribute box_type of plb_ddr_0_wrapper is "black_box";

module plb_tft_cntlr_ref_0_wrapper
  (
    SYS_plbClk,
    SYS_plbReset,
    Mn_request,
    Mn_ABus,
    Mn_RNW,
    Mn_BE,
    Mn_size,
    Mn_type,
    Mn_priority,
    Mn_rdBurst,
    Mn_wrBurst,
    Mn_busLock,
    Mn_abort,
    Mn_lockErr,
    Mn_msize,
    Mn_ordered,
    Mn_compress,
    Mn_guarded,
    Mn_wrDBus,
    PLB_MnRdWdAddr,
    PLB_MnRdDBus,
    PLB_MnAddrAck,
    PLB_MnRdDAck,
    PLB_MnWrDAck,
    PLB_MnRearbitrate,
    PLB_MnBusy,
    PLB_MnErr,
    PLB_MnRdBTerm,
    PLB_MnWrBTerm,
    PLB_Mnssize,
    PLB_pendReq,
    PLB_pendPri,
    PLB_reqPri,
    SYS_dcrClk,
    DCR_Ack,
    DCR_DBusOut,
    DCR_ABus,
    DCR_DBusIn,
    DCR_Read,
    DCR_Write,
    SYS_tftClk,
    TFT_LCD_HSYNC,
    TFT_LCD_VSYNC,
    TFT_LCD_DE,
    TFT_LCD_CLK,
    TFT_LCD_DPS,
    TFT_LCD_R,
    TFT_LCD_G,
    TFT_LCD_B
  );
  input SYS_plbClk;
  input SYS_plbReset;
  output Mn_request;
  output [0:31] Mn_ABus;
  output Mn_RNW;
  output [0:7] Mn_BE;
  output [0:3] Mn_size;
  output [0:2] Mn_type;
  output [0:1] Mn_priority;
  output Mn_rdBurst;
  output Mn_wrBurst;
  output Mn_busLock;
  output Mn_abort;
  output Mn_lockErr;
  output [0:1] Mn_msize;
  output Mn_ordered;
  output Mn_compress;
  output Mn_guarded;
  output [0:63] Mn_wrDBus;
  input [0:3] PLB_MnRdWdAddr;
  input [0:63] PLB_MnRdDBus;
  input PLB_MnAddrAck;
  input PLB_MnRdDAck;
  input PLB_MnWrDAck;
  input PLB_MnRearbitrate;
  input PLB_MnBusy;
  input PLB_MnErr;
  input PLB_MnRdBTerm;
  input PLB_MnWrBTerm;
  input [0:1] PLB_Mnssize;
  input PLB_pendReq;
  input [0:1] PLB_pendPri;
  input [0:1] PLB_reqPri;
  input SYS_dcrClk;
  output DCR_Ack;
  output [0:31] DCR_DBusOut;
  input [0:9] DCR_ABus;
  input [0:31] DCR_DBusIn;
  input DCR_Read;
  input DCR_Write;
  input SYS_tftClk;
  output TFT_LCD_HSYNC;
  output TFT_LCD_VSYNC;
  output TFT_LCD_DE;
  output TFT_LCD_CLK;
  output TFT_LCD_DPS;
  output [5:0] TFT_LCD_R;
  output [5:0] TFT_LCD_G;
  output [5:0] TFT_LCD_B;
endmodule

// synthesis attribute box_type of plb_tft_cntlr_ref_0_wrapper is "black_box";

module opb_ethernet_0_wrapper
  (
    PHY_tx_clk,
    PHY_rx_clk,
    PHY_crs,
    PHY_dv,
    PHY_rx_data,
    PHY_col,
    PHY_rx_er,
    OPB_ABus,
    OPB_DBus,
    OPB_errAck,
    OPB_BE,
    OPB_MGrant,
    OPB_retry,
    OPB_RNW,
    OPB_select,
    OPB_seqAddr,
    OPB_timeout,
    OPB_xferAck,
    Freeze,
    OPB_Clk,
    OPB_Rst,
    PHY_tx_en,
    PHY_rx_en,
    PHY_tx_er,
    PHY_tx_data,
    PHY_rst_n,
    Sln_xferAck,
    Sln_errAck,
    Sln_retry,
    Sln_toutSup,
    Sln_DBus,
    Mn_request,
    Mn_busLock,
    Mn_select,
    Mn_RNW,
    Mn_BE,
    Mn_seqAddr,
    Mn_ABus,
    emac_intrpts,
    IP2INTC_Irpt,
    PHY_Mii_clk_I,
    PHY_Mii_clk_O,
    PHY_Mii_clk_T,
    PHY_Mii_data_I,
    PHY_Mii_data_O,
    PHY_Mii_data_T
  );
  input PHY_tx_clk;
  input PHY_rx_clk;
  input PHY_crs;
  input PHY_dv;
  input [3:0] PHY_rx_data;
  input PHY_col;
  input PHY_rx_er;
  input [0:31] OPB_ABus;
  input [0:31] OPB_DBus;
  input OPB_errAck;
  input [0:3] OPB_BE;
  input OPB_MGrant;
  input OPB_retry;
  input OPB_RNW;
  input OPB_select;
  input OPB_seqAddr;
  input OPB_timeout;
  input OPB_xferAck;
  input Freeze;
  input OPB_Clk;
  input OPB_Rst;
  output PHY_tx_en;
  output PHY_rx_en;
  output PHY_tx_er;
  output [3:0] PHY_tx_data;
  output PHY_rst_n;
  output Sln_xferAck;
  output Sln_errAck;
  output Sln_retry;
  output Sln_toutSup;
  output [0:31] Sln_DBus;
  output Mn_request;
  output Mn_busLock;
  output Mn_select;
  output Mn_RNW;
  output [0:3] Mn_BE;
  output Mn_seqAddr;
  output [0:31] Mn_ABus;
  output [0:21] emac_intrpts;
  output IP2INTC_Irpt;
  input PHY_Mii_clk_I;
  output PHY_Mii_clk_O;
  output PHY_Mii_clk_T;
  input PHY_Mii_data_I;
  output PHY_Mii_data_O;
  output PHY_Mii_data_T;
endmodule

// synthesis attribute box_type of opb_ethernet_0_wrapper is "black_box";

module opb_emc_0_wrapper
  (
    OPB_Clk,
    OPB_Rst,
    OPB_ABus,
    OPB_DBus,
    Sln_DBus,
    OPB_select,
    OPB_RNW,
    OPB_seqAddr,
    OPB_BE,
    Sln_xferAck,
    Sln_errAck,
    Sln_toutSup,
    Sln_retry,
    Mem_A,
    Mem_DQ_I,
    Mem_DQ_O,
    Mem_DQ_T,
    Mem_CEN,
    Mem_OEN,
    Mem_WEN,
    Mem_QWEN,
    Mem_BEN,
    Mem_RPN,
    Mem_CE,
    Mem_ADV_LDN,
    Mem_LBON,
    Mem_CKEN,
    Mem_RNW
  );
  input OPB_Clk;
  input OPB_Rst;
  input [0:31] OPB_ABus;
  input [0:31] OPB_DBus;
  output [0:31] Sln_DBus;
  input OPB_select;
  input OPB_RNW;
  input OPB_seqAddr;
  input [0:3] OPB_BE;
  output Sln_xferAck;
  output Sln_errAck;
  output Sln_toutSup;
  output Sln_retry;
  output [0:31] Mem_A;
  input [0:31] Mem_DQ_I;
  output [0:31] Mem_DQ_O;
  output [0:31] Mem_DQ_T;
  output [0:1] Mem_CEN;
  output [0:1] Mem_OEN;
  output Mem_WEN;
  output [0:3] Mem_QWEN;
  output [0:3] Mem_BEN;
  output Mem_RPN;
  output [0:1] Mem_CE;
  output Mem_ADV_LDN;
  output Mem_LBON;
  output Mem_CKEN;
  output Mem_RNW;
endmodule

// synthesis attribute box_type of opb_emc_0_wrapper is "black_box";

module opb_gpio_exp_hdr_0_wrapper
  (
    OPB_ABus,
    OPB_BE,
    OPB_Clk,
    OPB_DBus,
    OPB_RNW,
    OPB_Rst,
    OPB_select,
    OPB_seqAddr,
    Sln_DBus,
    Sln_errAck,
    Sln_retry,
    Sln_toutSup,
    Sln_xferAck,
    IP2INTC_Irpt,
    GPIO_in,
    GPIO_d_out,
    GPIO_t_out,
    GPIO2_in,
    GPIO2_d_out,
    GPIO2_t_out,
    GPIO_IO_I,
    GPIO_IO_O,
    GPIO_IO_T,
    GPIO2_IO_I,
    GPIO2_IO_O,
    GPIO2_IO_T
  );
  input [0:31] OPB_ABus;
  input [0:3] OPB_BE;
  input OPB_Clk;
  input [0:31] OPB_DBus;
  input OPB_RNW;
  input OPB_Rst;
  input OPB_select;
  input OPB_seqAddr;
  output [0:31] Sln_DBus;
  output Sln_errAck;
  output Sln_retry;
  output Sln_toutSup;
  output Sln_xferAck;
  output IP2INTC_Irpt;
  input [0:31] GPIO_in;
  output [0:31] GPIO_d_out;
  output [0:31] GPIO_t_out;
  input [0:31] GPIO2_in;
  output [0:31] GPIO2_d_out;
  output [0:31] GPIO2_t_out;
  input [0:31] GPIO_IO_I;
  output [0:31] GPIO_IO_O;
  output [0:31] GPIO_IO_T;
  input [0:31] GPIO2_IO_I;
  output [0:31] GPIO2_IO_O;
  output [0:31] GPIO2_IO_T;
endmodule

// synthesis attribute box_type of opb_gpio_exp_hdr_0_wrapper is "black_box";

module opb_gpio_char_lcd_0_wrapper
  (
    OPB_ABus,
    OPB_BE,
    OPB_Clk,
    OPB_DBus,
    OPB_RNW,
    OPB_Rst,
    OPB_select,
    OPB_seqAddr,
    Sln_DBus,
    Sln_errAck,
    Sln_retry,
    Sln_toutSup,
    Sln_xferAck,
    IP2INTC_Irpt,
    GPIO_in,
    GPIO_d_out,
    GPIO_t_out,
    GPIO2_in,
    GPIO2_d_out,
    GPIO2_t_out,
    GPIO_IO_I,
    GPIO_IO_O,
    GPIO_IO_T,
    GPIO2_IO_I,
    GPIO2_IO_O,
    GPIO2_IO_T
  );
  input [0:31] OPB_ABus;
  input [0:3] OPB_BE;
  input OPB_Clk;
  input [0:31] OPB_DBus;
  input OPB_RNW;
  input OPB_Rst;
  input OPB_select;
  input OPB_seqAddr;
  output [0:31] Sln_DBus;
  output Sln_errAck;
  output Sln_retry;
  output Sln_toutSup;
  output Sln_xferAck;
  output IP2INTC_Irpt;
  input [0:6] GPIO_in;
  output [0:6] GPIO_d_out;
  output [0:6] GPIO_t_out;
  input [0:6] GPIO2_in;
  output [0:6] GPIO2_d_out;
  output [0:6] GPIO2_t_out;
  input [0:6] GPIO_IO_I;
  output [0:6] GPIO_IO_O;
  output [0:6] GPIO_IO_T;
  input [0:6] GPIO2_IO_I;
  output [0:6] GPIO2_IO_O;
  output [0:6] GPIO2_IO_T;
endmodule

// synthesis attribute box_type of opb_gpio_char_lcd_0_wrapper is "black_box";

module opb_sysace_0_wrapper
  (
    OPB_Clk,
    OPB_Rst,
    OPB_ABus,
    OPB_DBus,
    Sln_DBus,
    OPB_select,
    OPB_RNW,
    OPB_seqAddr,
    OPB_BE,
    Sln_xferAck,
    Sln_errAck,
    Sln_toutSup,
    Sln_retry,
    SysACE_MPA,
    SysACE_CLK,
    SysACE_MPIRQ,
    SysACE_MPD_I,
    SysACE_MPD_O,
    SysACE_MPD_T,
    SysACE_CEN,
    SysACE_OEN,
    SysACE_WEN,
    SysACE_IRQ
  );
  input OPB_Clk;
  input OPB_Rst;
  input [0:31] OPB_ABus;
  input [0:31] OPB_DBus;
  output [0:31] Sln_DBus;
  input OPB_select;
  input OPB_RNW;
  input OPB_seqAddr;
  input [0:3] OPB_BE;
  output Sln_xferAck;
  output Sln_errAck;
  output Sln_toutSup;
  output Sln_retry;
  output [6:0] SysACE_MPA;
  input SysACE_CLK;
  input SysACE_MPIRQ;
  input [15:0] SysACE_MPD_I;
  output [15:0] SysACE_MPD_O;
  output [15:0] SysACE_MPD_T;
  output SysACE_CEN;
  output SysACE_OEN;
  output SysACE_WEN;
  output SysACE_IRQ;
endmodule

// synthesis attribute box_type of opb_sysace_0_wrapper is "black_box";

module opb_emc_usb_0_wrapper
  (
    OPB_Clk,
    OPB_Rst,
    OPB_ABus,
    OPB_DBus,
    Sln_DBus,
    OPB_select,
    OPB_RNW,
    OPB_seqAddr,
    OPB_BE,
    Sln_xferAck,
    Sln_errAck,
    Sln_toutSup,
    Sln_retry,
    Mem_A,
    Mem_DQ_I,
    Mem_DQ_O,
    Mem_DQ_T,
    Mem_CEN,
    Mem_OEN,
    Mem_WEN,
    Mem_QWEN,
    Mem_BEN,
    Mem_RPN,
    Mem_CE,
    Mem_ADV_LDN,
    Mem_LBON,
    Mem_CKEN,
    Mem_RNW
  );
  input OPB_Clk;
  input OPB_Rst;
  input [0:31] OPB_ABus;
  input [0:31] OPB_DBus;
  output [0:31] Sln_DBus;
  input OPB_select;
  input OPB_RNW;
  input OPB_seqAddr;
  input [0:3] OPB_BE;
  output Sln_xferAck;
  output Sln_errAck;
  output Sln_toutSup;
  output Sln_retry;
  output [0:31] Mem_A;
  input [0:31] Mem_DQ_I;
  output [0:31] Mem_DQ_O;
  output [0:31] Mem_DQ_T;
  output [0:0] Mem_CEN;
  output [0:0] Mem_OEN;
  output Mem_WEN;
  output [0:3] Mem_QWEN;
  output [0:3] Mem_BEN;
  output Mem_RPN;
  output [0:0] Mem_CE;
  output Mem_ADV_LDN;
  output Mem_LBON;
  output Mem_CKEN;
  output Mem_RNW;
endmodule

// synthesis attribute box_type of opb_emc_usb_0_wrapper is "black_box";

