Data Sheets
MC14007 MOSFET Array
Application Notes
ECL Translator Guide
Analog Devices ADC Overview
PCB Layout
Ultracad PCB Design Articles
Transmission Line Theory (from Motorola ECL manual)
ECL Termination Guide (from Motorola ECL manual)
Signal Integrity (article from EDN)
Impedance of PCB Trace Transmission Lines (from Motorola ECL manual)
IC Design, Layout & Packaging
Analog and Mixed Signal Circuits On Digital CMOS Processes
by Jerry Twomey (a WPI alum!). Excellent practical tips.
1.0 mil Bondwire - Inductance, Capacitance and Resistance data
(from Amkor)
Bondwire Current Handling Capability PER MIL-H-38534
(from Amkor)
IC Design for Debugging
(from EDN Magazine)
Importance of designing in a "Built-in-Debug" capability in a new IC design
"How to Make a Chip" presentation
by Thomas Liechti (visiting researcher from EPFL, Lausanne, Switzerland, summer 2007)
0.25µm TSMC CMOS plots of g
m
, V
GS
, r
o
as a function of I
D
and W/L
Mismatch Papers:
Pelgrom MOS Mismatch analog CMOS Scaling 1998
Pelgrom MOS Mismatch JSSC 1989
Danaie BJT Mismatch 2006 Microelectronics Test Conf
Bordez BJT Matching at High Current Levels BCTM 2005
Einfeld BJT Mismatch 2004 Microelectronics Test Conf
Vadipour Optimum Degeneration for BJT Mismatch JSSC1994
Phase-Locked Loop / Oscillator Jitter / Noise
Jitter Course
Crystal Oscillator Design Notes
Phase Modulation Basics (from HP)
Bluetooth Specifications
Fibre Channel - Methodologies for Jitter and Signal Quality Specification - MJSQ
ISSCC2004 Practical PLL Design Tutorial
1/f Noise Web Page
Lab Equipment User Manuals
Tektronix DG2020A Timing Generator
Other Resources
Sample Lab Writeup
Contour plot of s-plane magnitude for 3-pole Butterworth filter
Establishing Ground Rules for Groups
Tutorial on FFT Windows (end effects, choice of window functions, etc.)
Papers
"Jitter and Phase Noise in Ring Oscillators," Ali Hajimiri, Sotirios Limotyrakis, and Thomas H. Lee, IEEE Journal of Solid-State Circuits, vol. 34, no. 6, June 1999